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SAN FRANCISCO—Intel will continue riding the bus route.
Executives at the chip maker, in a high-level discussion of its Core Microarchitecture at its spring Developer Forum, here, said that the companys bus approach—using a series of pipelines and a discrete controller to shuttle data between its processors and memory versus directly connecting the chips—still has legs.
Intels current chips and supporting platform designs use buses in combination with relatively large caches that store data onboard.
The approach has been widely criticized by rival Advanced Micro Devices as less efficient, particularly when it comes to power consumption.
Power, numerous Intel executives have said at the forum, is becoming paramount to all of its chip and system platform designs.
But, “By and large, when you look at the aggregate, we still have a lot of leg room” on the current design, which includes discrete memory controllers, said Steve Pawlowski, general manager of Intels Architecture and Planning group, in a briefing.
Intel, he said, has years of experience working with its bus-based system platform designs, which allows it to move platforms into the market more quickly.
Still, the chip maker has weighed whether or not to integrate a memory controller—it had planned to do so in integrated Timna chip for low-price PCs, but the chip was canceled—most recently within its first crop of Core Microarchitecture chips.
Those chips boast double-digit performance gains and, in desktops and servers, will use much less power as well.
But “As youve seen…so far were still not getting completely in the way of the processor” with the approach, Pawlowski said, citing Intels Bensley server platform as one example.
Bensley, Intels latest Xeon DP server platform, uses dual independent buses and twin memory channels for connecting to FB-DIMMs (fully buffered, dual-inline memory modules). Servers using the platform are expected in May or June.
“The total bandwidth of two buses and FB-channels…are equivalent,” he said. Some overhead comes from signals between processors.
But, “for the majority of the workloads…memory [bandwidth] hasnt gotten in the way yet.”
Thats not to say Intel wont go down the path of changing its bus designs—its gone on the record saying it will change its approach for servers—or even integrate a memory controller at some point.
“I can see some tech and some trends going forward, where were going to have to look at. Were certainly open to look at that when the time comes,” he said.
Intels forthcoming Tigerton server chip, for one, will use a new type of bus, which it has described as a point-to-point connection.
However, the chip maker has said the approach will not involve it adding an on-chip memory controller, nor will it be a new-generation interconnect that the company has said it is designing for future versions of its Itanium line of chips for big servers.
Poulson chip, which will be a follow-on to Intels 2008 quad-core Tukwila chip, will be the first to use the new interconnect—which will link it to components such as memory—Intel has said.
The interconnect will be used for both Itanium and Xeon chips at that time, the chip maker has indicated.
An Intel spokesperson declined to comment on how that connection will work, however.
Still, based on Pawlowskis statements, it appears that most of the companys x86 chips will continue using the bus and discrete memory controller in the future.
Right now, “The key is leverage capabilities we have to try to get to market as quickly as possible with the technologies we can bring to bear,” he said.