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Texas Instruments Inc. is the latest chipmaker to announce plans to manufacture chips using a process that creates structures that are even smaller than the already tiny transistors on processors in current PCs and mobile devices.
The company on Monday said it has already created 4M-bit test SRAM arrays based on the 65-nanometer manufacturing process and plans to sample a wireless product built with the new process in the first quarter of 2005, with manufacturing in late 2005.
The new chips will be half the size of 90nm designs and pack 40 percent greater transistor performance, according to TI.
If the Dallas-based chipmaker lives up to its promise, it will align with Moores Law, which predicts that the number of transistors per square inch of chip will double about every two years.
The transition from 90nm to 65nm should be easier than the jump from 130nm to 90nm, which the company made in 2003, TI spokesman Gary Silcott said.
“With 90nm we introduced the low-k dielectric material, but with 65nm theres not as much new innovation in terms of new materials being introduced,” said Silcott. “We look at this step as evolutionary rather than revolutionary.”
Silcott said the biggest challenge in moving to the 65nm level is power management. As more and more transistors are put onto a single chip, generating more and more heat, keeping power consumption low becomes a key concern.
“When you move to 65nm, transistors get smaller, materials get thinner, so you run up against what is called leakage,” Silcott said. “Even when transistors are off, they have a current that leaks through them.” If your cell phone battery has ever died while in standby mode waiting for a call, youve likely experienced this problem.
TI said new technology in its 65nm chips will reduce this leakage by 1,000 times. One of the most unique qualities of the technology is its ability to “automatically scale power supply volume to as low as possible when users dont need highest performance, and as users demand it boosts it up again,” Silcott said.
Next page: 65nm chips come in three flavors.
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TI plans to offer three versions of its 65nm chips: a low-power, lower-speed version geared for battery-powered wireless portable devices; a midlevel version that offers more speed, for application-specific products like DSPs; and a high-speed, microprocessor-class version for Sun Microsystems Inc. servers.
Silcott said multigate transistors wont be on the horizon for 65nm technologies. “Were looking at that for 45nm, or beyond,” he said. “45nm is expected to have some new material, potentially metal gates. … It will definitely be interesting.”
Intel Corp., of Santa Clara, Calif., last fall demonstrated 65nm SRAM chips and announced plans to manufacture chips based on the 65nm process in 2005. IBM is also on the 65nm wagon. The Armonk, N.Y., company last summer entered into a multiyear agreement with Infineon Technologies AG and Chartered Semiconductor Manufacturing to speed up the process of 65nm chip development. IBM previously teamed up with Advanced Micro Devices Inc. to develop 65nm and 45nm chip technologies on 300mm silicon wafers.
In a separate announcement Monday, TI unveiled its TNETW1250 technology, a new Wi-Fi chipset for cell phones, handhelds and other mobile devices.
The new chipset is smaller than TIs previous Wi-Fi chipsets and offers longer battery life, according to TI.
This year “is expected to be a pivotal year for Wi-Fi enabled portable devices, as more 802.11-enabled cell phones and PDAs hit the market,” said Marc Cetto, general manager of TIs Mobile Connectivity Solutions, in a statement. “The TNETW1250 platform will allow manufacturers to quickly deploy new 802.11a/b/g-enabled mobile devices that are smaller and offer maximum battery life.”
The chipset is set to ship midyear.
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