Advanced Micro Devices Inc. and IBM said Monday that they had developed a new strained-silicon process that offers more performance at the same power levels, a technology that will enter production in mid-2005.
Specifically, the new “Dual Stress Liner” technology has been found to deliver up to a 24 percent increase in transistor speed within the current power envelope, the two companies said. The strained-silicon process will be rolled out in AMDs first dual-core Opterons and in a new revision of IBMs Power chips, both due in the first half of next year.
The strained-silicon technology is designed to offer lower capacitance, or electrical resistance, to a charge as it passes through the gates of a transistor. Under normal conditions, the lower capacitance also results in a “leaky” transistor, which drains a trickle of power over time. This phenomenon will drain a laptop battery, for example, in standby mode.
The companies said that the new strained silicon process enhances the performance of both types of semiconductor transistors in semiconductors, called n-channel and p-channel transistors, by stretching silicon atoms in one transistor and compressing them in the other. The Dual Stress Liner technology can be integrated without the need for special processes or manufacturing materials, the two companies said, a reference to the silicon-germanium layer that Intel uses in its own SOI technology.