Advanced Micro Devices is determined to move its chips to 45-nanometer manufacturing by the end of 2008.
In a product road map released May 7, AMD indicated that it is planning to release the 45-nm “Shanghai” processor, which will contain four processing cores, sometime in the later part of 2008, although the chip maker is not offering a specific release date at this point. This processor will contain 6MB of Level 3 cache compared with the 2MB of L3 cache in the company’s current crop of quad-core Opteron processors.
As AMD looks toward 2009, it will release another 45-nm processor, “Istanbul,” which will contain six processing cores. In 2010, the company plans to release two additional processors, which will take advantage of new chip sets and newer DDR3 (double data rate 3) memory. The first, called “Magny-Cours,” will use 12 processing cores, and the second, “Sao Paulo,” will have six cores.
This particular road map addresses AMD’s chips for dual-socket and multisocket servers and workstations. The company did not offer updates on its PC or single-socket server plans, although a 45-nm desktop processor, “Deneb,” is slated for release in 2008.
The most important part of the road map for AMD, its partners and customers is the switch from the company’s current 65-nm production to 45-nm later in 2008. The advantages to switching to 45-nm production are numerous and the change should allow AMD to produce smaller processors with greater performance that use less power.
It will also allow the company to move to new chip technologies such as combining the CPU and GPU (graphics processing unit) on a single piece of silicon in what the company calls an Accelerated Processing Unit.
The new road map also means that AMD is prepared to stay competitive against Intel in the high-end multiprocessor system market. For its part, Intel is preparing to release its own six-core processor for MP servers later in 2008 before it switches to a new microarchitecture called “Nehalem.”
With Nehalem, Intel plans to erase several advantages AMD has with its Opteron processor. These improvements from Intel will include a new high-speed chip-to-chip interconnect and an integrated memory controller.
For now, AMD is looking to move past some of the problems that delayed the release of its quad-core Opteron processor “Barcelona” in late 2007. In the last few months, Hewlett-Packard and Dell have each announced new systems based on the chip and Sun Microsystems, IBM and Fujitsu Siemens Computers are expected to follow suit.
One reason Barcelona’s problems initially went undetected was that AMD did not provide samples to system vendors earlier in the production process. This meant that design flaws in the silicon went unreported until later in the year.
In its effort to correct the mistakes of 2007, the company has already begun shipping samples of Shanghai to its OEM partners for testing and validation, according to Randy Allen, corporate vice president of AMD’s Server and Workstation Division.
In addition, all the new processors AMD detailed May 7 are derivatives of the microarchitecture used with the current four-core Opteron chip. This means that any problems with the silicon should be fixed.
“Shanghai is a derivative of Barcelona, so it doesn’t have anywhere near the level of logic complexity that Barcelona represented because it leverages very highly from the Barcelona core development,” Allen said. “We are also engaging our OEM partners in the system validation early on so that we can incorporate any insights or findings that they have. In order to accelerate time to market, the key is finding any bugs or issues as soon as you can and then you have more runway to incorporate those changes. The thing that kills you is finding a problem late in the game, and that’s what happened with Barcelona.”
So far, Allen said the feedback from AMD’s OEM partners has been positive.
Allen added that while AMD is developing a new x86 microarchitecture-“Bulldozer”-the chips listed in this road map do not contain that new technology. The road map also did not include a timeframe for the company’s transition to 32-nm manufacturing.
