SAN FRANCISCO-Intel lifted the curtain a little more on its upcoming lineup of processors based on the “Nehalem” microarchitecture, which will include new power management features and enhanced capabilities for virtualization.
While the chip maker held back some critical information on the Nehalem-based processors, such as clock speeds and pricing, an Intel executive did announce a new power management feature called TurboMode, which will allow for dynamic power management within the silicon itself. The other significant update is a virtualization technology dubbed VTD, which dedicates I/O resources for virtual machines.
These details were announced at the start of Intel Developer Forum, which kicked off Aug. 19.
The Nehalem microarchitecture represents a significant step forward for Intel processors, especially for those chips destined for servers. These upcoming Intel processors will have the ability to scale from two to eight cores and feature a number of technologies that Intel has talked about in the last 12 months, including a high-speed chip-to-chip interconnect called QuickPath and an integrated memory controller. Intel’s main rival, Advanced Micro Devices, has used an integrated memory controller with its Opteron processors for the last five years.
The clock speeds of the Nehalem processors are expected to be similar to those offered with the current crop of 45-nanometer Xeon and Core 2 Duo processors. Instead of touting the clock speeds, Intel decided to emphasize the power efficiency of the processors and their ability to handle virtualization technology.
“It’s not raw horsepower any more,” said Jim McGregor, an analyst with In-Stat. “It’s about what are the tweaks that I can [make] efficiently. So, it gets down to … doing things as efficiently as possible. At the same time, the whole electronics paradigm has shifted and now power is king and they’re still pushing [the] envelope of performance.”
The other improvement to power efficiency is what Intel calls Hyper-Threading Technology, which allows for two instructional threads per core. A four-core Nehalem processor, for example, offers a total of eight threads. When combined with TurboMode, a server can run a single-threaded application with much greater power efficiency since the other cores can power down. At the same time, the clock speed also goes up, which gives a bump in performance.
When a system has multithreaded applications, all the cores and all the threads can come on at once.
The first of the Nehalem processors will arrive in the fourth quarter of 2008, and Intel will initially target gamers and PC enthusiasts with a chip called the Intel Core i7 for desktop PCs. Intel also showed the first eight-core Nehalem-EX processor, which will be geared toward servers and is expected to arrive early in 2009.
“Nehalem is the world’s first dynamically scalable architecture,” said Patrick Gelsinger, senior vice president at Intel and the general manager of the Digital Enterprise Group.
More Coming from Intel
In addition to these processors, Gelsinger announced several upcoming Nehalem-based chips, including one for high-performance computing dubbed Nehalem-EP and a number of desktop chips with the code names Havendale and Lynnfield, and notebook processors with the code names Auburndale and Clarksfield.
While Gelsinger did not delve into specific details of when all the new Nehalem processors would ship, after the high-end desktop models come to market Intel is expected to follow with chips for single-socket servers and then for two-socket systems. AMD, which is preparing a new 45-nanometer processor, wants to compete against Intel in the two-socket system space and its executives believe it will deliver the chip to this market before Intel does.
The types of power management features that Intel talked about at IDF have been around for a number of years. What is different with Nehalem is a technology Intel calls Power Gates, which not only allows for the cores to turn on and off, but further reduces leakage-the electricity that is wasted while the transistors sit idle. To achieve this, Intel incorporated power sensors into Nehalem to monitor power use and built an integrated microcontroller into the chip.
While these developments were noteworthy, the opening of IDF lacked a big-bang moment. This is due in part to the fact that many Nehalem details, from the integrated memory controller to the chip-to-chip interconnect, had already been disclosed by Intel in the months leading up to IDF. At the same time, since most of the Nehalem processors will not ship until the fourth quarter, Intel held back pricing and clock speed details.
Other Nehalem details that came to light during the opening of IDF included the processor’s support of new DDR3 (double data rate) memory and the use of 8MB of Level 3 cache that will be shared across all the cores.
In addition to Nehalem, Gelsinger announced that Intel’s “Dunnington” processor, a six-core, 45-nm processor for multisocket servers, will ship in September. The first of these processors, the Xeon X7460, will feature 16MB of L3 cache. IBM, Hewlett-Packard, Dell, Sun Microsystems and Fujitsu-Siemens are all expected to release servers based on the Dunnington processors.
The opening keynotes also went over details Intel had released regarding its “Larrabee” processor for dedicated graphics.
