SAN FRANCISCO-Advanced Micro Devices is preparing to release a new server platform in the second half of 2009, now code-named Fiorano, which will take advantage of chip maker’s upcoming 45-nanometer processor called “Shanghai.”
On the eve of the 2008 Intel Developer Forum here, AMD is trying to make some noise about its own product lineup, as Intel prepares to release the first of its Nehalem processors that will use a new microarchitecture and feature improvements such as a high-speed chip-to-chip interconnect and an integrated memory controller. These two features should offer a decent increase in the overall performance of the processors.
AMD announced Aug. 15 that its 45-nm chips would ship by the fourth quarter of 2008 and compete against the first patch of Intel processors based on Nehalem. AMD also began doling out details of its upcoming Fiorano platform on Aug. 18, which will use the 45-nm chip, fully support the company’s own chip-to-chip interconnect technology called HyperTransport 3 and offer a new virtualization technology. This technology, aka IOMMU, allows for virtualization of the system’s I/O traffic.
Fiorano is also the first time AMD will build its own chip set for servers after using chip sets from Nvidia and Broadcom for years.
In less than a week, AMD has begun detailing how it intends to bounce back in its ongoing fight with Intel and after it stumbled badly in bringing its quad-core Opteron chip into the market in late 2007 and early 2008. This comeback strategy involves beating Intel with its graphics technology and using the 45-nm Shanghai processor to compete against Intel’s Nehalem chip in the high-volume two- and four-socket server space.
While AMD has also been able to compete in the multisocket server space, Intel’s use of an integrated memory controller, which AMD has been using with Opteron, might erase some of that advantage. One reason AMD is pushing hard in this part of the server market is to protect its share of that market against an Intel onslaught.
While AMD has been willing to talk strategy, the company has not offered much in the way of details about Shanghai. What is known is that this AMD processor will have four processing cores, have 6MB of L3 cache and some of the 45-nm chips will support HyperTransport 3, but that depends on the type of system the processors are used in.
John Fruehe, who handles worldwide channel market development for AMD’s Server and Workstation Division, said Shanghai will offer a performance bump of between 15 and 30 percent, but did not offer more specifics. The Shanghai chip will also offer some improvements in instructions per cycle, which should help increase that performance.
“You wouldn’t expect 45-nm to be running hotter, and you wouldn’t expect it to be running slower, and you wouldn’t expect it to be more expensive,” Fruehe said. “So if you look at 65-nm compared to 45-nm, there is a definitive opportunity for improvements in performance, power and price.”
One reason AMD is holding back information on the 45-nm processors is a pure businesses decision. Since the original quad-core processor came to market late, AMD does not want its customers waiting to buy the new and improved 45-nm chips and ignoring the current 65-nm parts that are in the market now.
The one advantage that AMD believes it has coming into 2009 is that Shanghai will fit into the existing Socket F (1207) design that is used to support the current quad-core Opteron processors. The upcoming Fiorano platform will also support the Socket F design, which means customers only need a BIOS upgrade to use the newer chips.
With Nehalem, Intel is likely to require new chip sets to support this next generation of processors. This means OEMs will have to build new systems that need to be tested before heading to market.
The AMD Fiorano platform will also support the second generation of PCI Express.
AMD is also planning to support DDR2 (double data rate 2) memory with the Fiorano platform. Intel plans to upgrade to DDR3 with Nehalem, and AMD plans to wait until at least 2010 to offer support for DDR3. Fruehe explained that AMD believes DDR3 will remain too expensive for customers to invest in, and many IT buyers will wait until memory prices drop before adopting DDR3.
“It will hit once the price of DDR3 comes down,” Fruehe said. “The back half of next year  is about the time the process changes in DDR3 will happen that will allow the prices to come down.”
The first AMD platform to use DDR3 memory will be called “Maranello,” which was previously called “Piranha.”
AMD also has several new chips scheduled for release in 2009 after Shanghai hits the market later this year. These new AMD processors include another 45-nm processor, “Istanbul,” which will contain six processing cores. In 2010, the company plans to release two additional processors, which will take advantage of the Maranello chip set. These include “Magny-Cours,” which will use 12 processing cores, and “Sao Paulo,” which will have six cores.