64-Bit CPUs: What You Need to Know - Page 15

: How Itanium Handles x86 Code">

Yes, Virginia, there is an x86-compatibility mode in Itanium. Its awkward and unnatural, but we know how attached you are to your old binaries. IA-64 does not normally support older x86 binaries, and its entirely possible that some future IA-64 implementation might drop this feature or water it down, but for now your old Lotus 1-2-3 diskettes are safe.

Itanium supports all x86 instructions in one way or another, even MMX, SSE (not SSE2), Protected, Virtual 8086, and Real mode features. You can even run entire operating systems in x86 mode, or just run the applications under a new IA-64 OS. All the x86 registers map onto Itaniums own general-purpose registers, but some of the less orthogonal x86 registers appear in Itaniums "application registers" AR24 through AR31.

x86 mapping onto IA-64 registers

Switching modes appears trivial but isnt. Theres one IA-64 instruction that switches the processor to x86 mode and another (newly defined) x86 instruction, JMPE, that switches to IA-64 mode. If the programmer so wishes, interrupts can switch automatically to IA-64 mode or the machine can stay in x86 mode. In the latter case, you can reuse your x86 interrupt handlers.

Switching to x86 mode is a lot like booting a 386 because you have to set up memory segment descriptors, status registers, and flags. Also, x86 code likes to have its way with all the resources of the processor, either overwriting or ignoring many of Itaniums state bits and registers. Its also likely to upset your cache contents. In general, its best to save the entire state of the processor before switching to x86 mode. Its awkward enough that you probably dont want to switch modes willy-nilly. Save it for dramatic changes, such as executing entire x86 applications.

Not that anyone was asking, but PA-RISC compatibility is handled offline through a software translator. IA-64 instructions dont directly support PA-RISC instructions, but they do map fairly closely (hey, RISC is RISC). The fact that x86 binaries are emulated in minute detail with enormous helpings of hardware while PA-RISC code is relegated to a translator before it has any hope of running says a lot about the relative importance of these two installed bases. It may also tell us something about the "equal" relationship between the HP and Intel engineers designing IA-64.