64-Bit CPUs: What You Need to Know - Page 17

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The second IA-64 processor after Itanium is code-named McKinley and its likely to be faster, smaller, and all-around better than its predecessor. McKinleys L1 caches will be the same size as Itaniums, but the L2 cache will grow from 96K to 256K. The L3 cache will get smaller (3M instead of 4M) but move onto the actual chip, not just on the same cartridge. All three cache interfaces will get faster. McKinley shaves one cycle off the L1 cache access time (from two cycles to one), shortens L2 access time by seven cycles (to five), and takes eight cycles off the L3 latency (to 12 cycles). Adding the L3 cache to the chip will boost McKinleys die size significantly, probably to around 450 mm2, and ups the transistor count to 221 million. But manufacturing cost should be significantly reduced without the external L3 SRAMs and larger package required for the dual-chip (core and L3) Itanium.

McKinley will use a completely different socket design from Itanium and a revised bus interface, dooming the first IA-64 systems almost before they get out the door. Just like Pentium Pro, Itaniums mechanical footprint will be an orphan from Day One. McKinleys system bus will widen to 128 bits (up from Itaniums 64) and its clock frequency will improve from 133 MHz to 200 MHz. The bus will still be double-pumped (i.e., transferring data on both rising and falling edges of every clock) yielding 6.4GB/sec front-side bus bandwidth.

Next up comes Madison, expected to be a 0.13-micron shrink of McKinley, all other things being equal. Deerfield, the fourth member of IA-64s growing family, will also be a 0.13-micron shrink of McKinley, but this time with a smaller 1M L3 cache and yet another new bus interface intended for cheaper systems. Deerfield will be the "value" version of IA-64, à la Celeron or Duron.