64-Bit CPUs: What You Need to Know - Page 4

The Itanium processor has a massive register set, with 128 general-purpose integer registers (each 64 bits wide), 128 floating-point registers (each 82 bits wide), 64 1-bit predicate registers, 8 branch registers, and a whole bunch of other registers scattered among several different functions, including some for x86 backward compatibility. Like a lot of RISC processors, the first register (GR0) is hard-wired to a permanent zero, making it worthless for storage but useful as a constant for inputs and a bit bucket for outputs.

Heres a simplified diagram of key application registers:

IA-64 register set

Heres a detailed diagram of application and system-level register sets:

Application Register Set

And of course Itanium supports standard 32-bit x86 execution modes and the 32-bit registers are mapped onto the IA-64 registers. See details in the section titled "Dont Look Back: How Itanium Handles x86 Code" down below.

What a far cry from the cramped, crowded register set of the x86! With 256 registers to play with, programmers have an embarrassment of riches. To avoid that embarrassment, IA-64 has two features that manage the register file: register frames and register rotating. These require some explanation…