Intel may have found its transistor of the future.
The companys researchers feel that the combination of a three-dimensional or tri-gate transistor, which combines the use of advanced materials and manufacturing techniques, could be the answer to delivering future chips that are both speedy and energy efficient processors, Intel researchers said in a presentation at the VLSI Symposium on Technology and Circuits, which began on June 12.
During a discussion of their work, the researchers said using tri-gate transistors built using its mixture would allow them to continue keeping pace with Moores Law—the tenant that says chip transistor counts will double every two years and thus increase performance—for at least several more chip generations.
“That combination of this [transistor design, material and manufacturing techniques] is really what makes it special,” said Mike Mayberry, Intel vice president and director of component research, in Honolulu, Hawaii.
The tri-gate design discussed at the conference pairs high-k (high electrical capacitance) gate dielectrics, along with metal gates electrodes and a manufacturing technique called strained silicon offered to cut power consumption.
Transistors have a source, a drain and a gate. The channel, linking the source and drain, provides the path for electricity to follow between them.
The metal gate electrode, in this case, works to keep electricity inside the channel—the path between the source and drain—while strained silicon, which manipulates the silicon lattice the chip is built upon, speeds up the flow of electrons inside the chip.
Although he characterized the tri-gate option as one option Intel researchers have developed, Mayberry said that the combination can be used to help chips stay within their power consumption targets even as they move to new manufacturing levels.
Those transitions allow each chip pack on more transistors—and therefore boost performance—by arranging them more closely.
Intel researchers, tasked with keeping the chip maker on pace with Moores Law, continually look ahead for potential barriers. One such barrier, called the short channel effect, can be mitigated by the tri-gate design that researchers have created, Mayberry said.
The short channel effect comes into play as planar transistor gate widths shrink to minute proportions. Eventually, electricity, in standard planar transistor designs, finds it easier and easier to circumvent the gate and so-called leakage current increases—or the amount of energy burned when a transistor is in the off position.
“If we didnt do the research ahead of time…then if we got to a particular place wed be stuck,” Mayberry said.
Thus researchers turned to the tri-gate design, which surrounds the channel on three of four sides. The tri-gate transistor, its specific mix of material and the use of strained silicon all work together to block the short channel effect and thus allow the transistor to operate more efficiently.
Ultimately, “It allows you to turn the device off more strongly and off more cleanly,” Mayberry said. “Plus leakage through that is significantly reduced.”
When optimized for sheer speed, transistors using the design can run up to 45 percent faster than Intels current state-of-the-art 65 nanometer transistors, he said. Yet, when optimized for power, they can cut leakage by 50 times.
An in-between position would see the transistor using 35 percent less power while running at the same frequency, according to tests on proof-of-concept SRAM (static random access memory) cells, he said.
Still, while it shows great promise, the transistor design has not been officially adopted for use in products. Intel researchers can offer the new design to its manufacturing group responsible for implementing each new manufacturing technology transition, but the group would have to select the approach.
It has not decided one way or the other, just yet, Mayberry indicated.
“Weve not made the decision for which [manufacturing] node it will go in,” he said.
Intels 45-nanometer manufacturing, due in 2007, will not use the new transistor design. Although it is a strong candidate for 32-nanometer or 22-nanometer manufacturing processes, scheduled to arrive in 2009 and 2011, respectively, he said.
