Intel Will Talk Silverthorne at Chip Conference

At the ISSCC show, the chip maker will offer more details about its new processor for mobile Internet devices.

Intel will pull back the curtain on Silverthorne just a little more at the International Solid State Circuits Conference in San Francisco, which started Feb.3.

The chip maker will present more than a dozen technical papers that will range from a first look at its new quad-core Itanium processor to developments in new memory technology to an update on Intel's tera-scale processor.

However, Intel will focus most of its attention on Silverthorne, which has been designed for what Intel executives call mobile Internet devices or MIDs. Since the 2007 Intel Developer Forum, company officials have been talking about the new 45-nanometer processor, but the ISSCC conference marks the first time the company's engineers will talk about Silverthorne's technical properties.

In an interview before the start of the ISSCC, Intel Senior Fellow and Chief Technology Officer Justin Rattner said that Silverthorne is a whole new chip built on the Intel Architecture and able to perform at a sub-one watt level, which means it uses 10 times less power than Intel's ultra-low volt processor that uses about five watts of power.

The Silverthorne processor also contains Intel's deep power-down technology and a split I/O power supply that Rattner said will allow for "much finer grain power management." However, he did not discuss a specific clock speed or a specific performance per watt for Silverthorne.

"We believe that it's a very impressive device," Rattner said. "It has a very dynamic range, especially for a processor that can be active and operating at a sub-one watt level."

Silverthorne has also been designed with an in-order instructional pipeline. Unlike an out-of-order pipeline that breaks data apart and allows for instructions to run in parallel, an in-order pipeline means the core will have to accept one set of instructions first before moving onto the next step. With Silverthorne, the chip will support two instructional threads, which will then allow two instructions to pass through with each cycle.

Intel's technical paper did note that it would contain 512KB of L2 cache.

John Spooner, an analyst with Technology Business Research, said that building Silverthorne with an in-order pipeline means the processor will give up some performance. However, those types of tradeoffs are necessary when building a chip that uses less than two watts of power and for devices for users who want longer battery life.