Irish security vendor Accelerated Encryption Processing Ltd. on Monday will unveil two additions to its line of SSL accelerators, including a chip that can handle as many as 10,000 transactions per second.
The AEP10K is the first release under the companys new Scaleable Public Key Architecture, a design that will eventually support ASICs (application specific integrated circuits) capable of handling 100,000 Secure Sockets Layer handshakes per second. AEP will also announce on Monday the general availability of its Shared Encryption Processor.
The company will demo both chips at the RSA Conference in San Jose, Calif., Feb. 18 through 22.
The Shared Encryption Processor is based on the companys AEP2000 accelerator card and is designed to enable multiple servers on a network to share an accelerator. AEP will sell the chips to OEMs, who will then install them in Intel Corp. boxes and sell the finished product as an appliance.
The card supports both Windows and Linux, and up to four of the processors can be installed in a single appliance. Customers can then cluster as many as 16 appliances, which would deliver 128,000 transactions per second. The SEP ships with server software.
SSL transactions are notoriously slow compared with normal HTTP traffic, and with more and more Web sites delivering secure content, SSL accelerators are all but mandatory for Web site operators.
AEP, based in Dublin, Ireland, is also counting on the continued growth of the wireless networking market to drive demand for its chips.
“The world will become wireless, and everything will have to be encrypted,” said William Conner, executive vice president of AEP. He added that some governments in Europe are advocating an increase in the standard key size for RSA encryption to 2,048 bits from the current 1,024.
Such a large key size would require four times the processing power needed to process 1,024-bit keys, Conner said.
The AEP10K, meanwhile, is compatible with wire-speed Gigabit Ethernet and will be available in the second quarter of this year.
“The AEP10K has a compact and efficient design. I expect this architecture could scale to at least 100,000 RSA operations per second using currently available IC manufacturing technology,” said Linley Gwennap, principal analyst at The Linley Group in Mountain View, Calif.
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