New process marks a
departure for Intel"> One Intel watcher called the creation of a new process technology unique. "As long as weve been tracking Intel its never called out a completely separate [manufacturing] process like this," said Kevin Krewell, editor-in-chief of the Microprocessor Report.Paul Otellini, Intels CEO, showed off a concept for a small handheld computer he said could utilize ultra-low power Intel x86 processors at its Intel Developer Forum in September. Bohr indicated that the process would compliment low-power processor designs, including a including a project called LPIA or low power Intel architecture thats under way. However, P1265 is expected to be used mainly in products such as notebook chipsets at the outset. Click here to read more about Intels fall Developer Forum. The P1265 process, which Bohr said will enter into volume production in 2007, is far along in development by chip manufacturing standards. Intel has already created a fully functional SRAM (static random access memory) chip using it, a measure that Bohr said shows its viability. Intel traditionally uses SRAMs to test new manufacturing processes. The low-power process, meanwhile, is similar enough to Intels standard 65-nanometer process that both can be used on the same production lines with the same chip manufacturing machines. Instead of wholesale changes, which would force Intel to alter its manufacturing methods substantiallya time consuming and costly effortthe new process only changes a few steps of the manufacturing process. It essentially alters the recipe that the chip manufacturing tools follow in order to create each chip, Bohr said. The P1264 process and its low power P1265 derivative "were both developed in the same fab" or chip making factory, he said. "They both use the same equipment set, and most of the process steps are identical." Thus, a P1267, which mirrors Intels 45-nanometer P1266 process could arrive as well, sometime after 2007. Check out eWEEK.coms for the latest news in desktop and notebook computing.
"This divergence of the processes technologies, starting at 65-nanometer is an acknowledgement that standard logic process just isnt going to be optimized for battery powered devices. You have to trade off some performance for battery life."