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By Jeffrey Burt  |  Posted 2006-10-10 Print this article Print

Engineers at AMD, of Sunnyvale, Calif., will talk more about their upcoming quad-core Opteron processor, code-named "Barcelona," which is due in the first half of 2007. Among the enhancements AMD is making is widening the SSE engine from 64 bits to 128 bits, which will reduce the bottlenecks in instruction and data delivery, a key for high-performance computing workloads, said Ben Sander, principal member of the technical staff at AMD. Barcelona also will offer a Level 3 cache that will be shared by all the processing cores, which will complement the L2 cache that each core has. The shared cache will be particularly beneficial to large applications that need access to the same data stored there, said Chuck Moore, a senior fellow at AMD. IBM hopes to boost market share by selling quad cores for the price of current chips. Click here to read more.
Other enhancements include better DRAM efficiency through independent controllers and larger buffering in the Northbridge and memory controller, Sander said. Also, virtualization support and security are improved, making application performance in virtualized environments "closer to native performance" in physical servers, Sander said.
Power management features include separate power planes for the processing core and integrated Northbridge, which enables the cores to throttle down power depending on application demand while keep the Northbridge powered up. In addition, with an enhanced PowerNow offering, each core can be dynamically controlled depending on workload demand. AMDs presentation will come a month after rival Intel outlined its quad-core plans at its fall developer forum. Intel announced plans to bring its first quad-core chips to market this fall. A key difference is Intels initial quad-core chips will essentially feature two dual-core chips on a single piece of silicon, enabling the chip maker to beat AMD to market. However, AMD officials have argued that the companys native quad-core chips with its on-board memory will be more elegant and efficient than Intels offerings. Also presenting at the Microprocessor Forum Oct. 10 will be Sun and Fujitsu. Sun, of Santa Clara, Calif., will outline plans for "Niagara 2," the follow-on to its multicore UltraSPARC T1 processor. Like the first Niagara, Niagara 2, due next year, will feature up to eight cores. However, each core will be capable of running up to eight instruction threads simultaneously, doubling the capacity of the current chip. For Tokyo-based Fujitsu, its upcoming Sparc64 VI will be its first dual-core offering and will be the basis for the upcoming Advanced Product Line of servers, developed jointly with Sun. Check out eWEEK.coms for the latest news, views and analysis on servers, switches and networking protocols for the enterprise and small businesses.


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