eWEEK content and product recommendations are editorially independent. We may make money when you click on links to our partners. Learn More.
A group of industry heavyweights, including Dell EMC, Hewlett Packard Enterprise, IBM, ARM and Lenovo, is launching an alliance to develop a scalable computing interconnect and protocol that will enable systems to keep with the rapidly rising tide of data that is being generated and that needs to be analyzed.
The new industry group, the Gen-Z Consortium, is working to create a flexible, high-performance and low-latency memory semantic fabric that can enable systems to more easily and quickly move and access large amounts of data. Consortium leaders expect to see products using the new Gen-Z interconnect by 2018.
The new alliance comes as vendors try to address the need for new memory and storage capabilities in light of such trends as the internet of things (IoT), cloud computing and real-time data analytics. The highest profile of such efforts is Intel’s work with Micron Technology on its 3D Xpoint memory architecture and the Optane memory chips based on the architecture. Both were introduced by Intel officials last year.
According to Gen-Z officials, computers traditionally have been built with the idea that storage is slow but persistent and reliable, and that data housed in memory is fast but volatile. The push now is to converge the attributes of both storage and memory and improve data access at the rack level.
“The vision behind Gen-Z is to solve the growing challenges associated with processing and analyzing huge amounts of data in real time while avoiding today’s system bottlenecks,” Ron Noblett, vice president of the Advanced Architecture Development CTO Group at Hewlett Packard Enterprise (HPE), wrote in a post on the company blog. “The idea is to get back to the most basic functions that move data from one location to another. Gen-Z aims to get any device to communicate with any other device as if it were communicating with its own local memory using simple commands. Thus, we refer to it as a ‘memory semantic protocol.’ You can connect vast numbers of components together in the same fabric and each can get equal access to the data.”
The Gen-Z Consortium was launched by 20 vendors, including Advanced Micro Devices, Broadcom, Huawei Technologies, Red Hat, Micron, Xilinx, Samsung and Cray. Other founding members are Cavium, IDT, Mellanox Technologies, Microsemi, Seagate, SK hynix and Western Digital.
“Gen-Z is addressing the need for higher-performance data accesses, with an interconnect based on memory operations that addresses both server node and rack scale,” Jeff Defilippi, product manager at ARM, wrote in a post on the company blog. “Today, storage requires block-based accesses with complex, code-intensive software stacks. Memory operations such as loads and stores allow processors to access both volatile (ie DRAM) and non-volatile storage in the same efficient manner. Emerging Storage Class Memory (SCM) and rack level disaggregated memory pools, are example use-cases that benefit from a memory operation interconnect.”
According to the new group, Gen-Z will include a simplified interface based on memory semantics that will be able to scale from tens to several hundred GB/s of bandwidth, with a memory latency of less than 100 nanoseconds. In addition, it will enable what officials call “data-centric computing with scalable memory pools and resources” that will allow for real-time analytics and in-memory applications and drive the development of new memory and storage innovations.
It also will be compatible with a wide range of software and will scale to address everything from simple and low-cost connectivity to rack-scale interconnect.
“Today, each computer component is connected using a different type of interconnect,” HPE’s Noblett wrote. “Memory connects using DDR, hard drives via SATA, flash drives and graphics processing units via PCIe, and so on. At the simplest level, Gen-Z is focused on developing a new interconnect and protocol that can be used to replace all of those with a single, open, high-performance interconnect.”
That interconnect will be published and free of charge, and there will be no constraints on its reuse, according to consortium members. The core specification, which will include the architecture and protocol, will be finalized later this year, they said.