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Officials with startup Flex Logix Technologies believe they have a developed a way of making a better FPGA.
Field-programmable gate arrays are chips that can be reprogrammed to run a wide array of applications, giving hardware and software makers greater flexibility in the workloads that run in systems. Essentially, the chip can be configured to run one workload, then reprogrammed to run another, a capability that is in growing demand in Web-scale data center environments run by the likes of Facebook, Google and Microsoft, where the demands and workloads change rapidly.
It’s grown into a $5 billion industry that is dominated by the likes of Xilinx and Altera. However, Flex Logix officials believe they have found a way to enable chip makers to more effectively and cheaply reap the benefits of FGPAs, in large part by putting the technology directly onto the chip rather than house it as discrete silicon next to the chip.
“We want to build a better FPGA,” CEO Geoff Tate, founder and former CEO of computer memory chip maker Rambus, told eWEEK. “Everything else is being integrated into SoCs [systems-on-a-chip]. Why aren’t FPGAs being integrated? There is a lot of interest in this.”
Flex Logix is coming out of stealth mode Feb. 23, the same day that its co-founders and engineers—Cheng Wang, vice president of engineering, and Principal Hardware Designer Fang-Li Yuan, who’s principal hardware designer—and Dejan Markovic, technical advisor and electrical engineering professor at UCLA, are due to receive the Lewis Award for Outstanding Paper at the International Solid State Circuits Conference (ISSCC).
The company is looking to address the costs associated with chip design and manufacturing, according to Tate. He noted the growing costs of chip designs, and said that missing a product cycle can means millions of dollars in missed revenues. Upgrading chips can cost $2 million to $5 million, and the lack of chip programmability forces end users and hardware makers to replace systems when changes need to be made. Chip makers also are forced to offer too many options of the same chip in order to facilitate flexibility, Tate said.
PCs, servers and other computing systems traditionally have been powered by chips that have already been built by the likes of Intel, Advanced Micro Devices and Nvidia, creating a relatively set hardware environment that hosts software, which is where any flexibility for systems has come in. However, due to such trends as mobility, big data, hyperscale computing, the Internet of things (IoT) and the cloud, organizations and end users are demanding ever greater levels of flexibility, and tech companies are looking for ways to respond.
Intel over the past several years has been growing the number of chips offered in its processor releases to give organizations more options for optimizing the hardware for particular workloads. In addition, the company has been ramping up its custom chip business, including by putting FPGAs into the same package as its Xeon server chips. For their part, Microsoft officials last year announced Project Catapult, in which the software giant said it was going to leverage FPGAs in their servers to improve the performance of Bing workloads by up to 95 percent.
However, that comes at a cost—they increase power consumption and are expensive, according to Tate. Because of that, FPGAs are normally used for high-end workloads, he said.
Flex Logix’s technology will change the equation, he said. Instead of creating another discrete chip, the company’s technology will be offered as an IP block on the SoC, similar to the CPU, memory and I/O also housed in the system-on-a-chip. In addition, Flex Logix won’t make its own products; instead, the technology will be licensed to chip makers that can use them however they want. It’s similar to ARM’s business model, where the company designs the SoC architecture and licenses it to manufacturing partners like Samsung, Qualcomm, AMD and Nvidia.
Startup Flex Logix Aims to Make Chips More Programmable
Flex Logix is unveiling its EFLX FPGA technology, which leverages a network that is unlike the mesh networks used in most other FPGAs on the market. The hierarchical network design makes the EFLX more efficient and faster in moving data by reducing the length of communications links between logic blocks, which helps speed up software performance while improving energy efficiency, Tate said. It also cuts in half the area needed for the interconnects and reduces the number of metal layers, which enables the EFLX cores to be integrated into other devices.
In the FPGA world, the devices are measured by LUTs, or lookup tables, which are collections of programmable circuits that can be linked together. Flex Logix is using a basic design that offers 100 LUTs and another with 2,500 LUTs, with a 10,400 LUT model on the way. In addition, those units can be layered to create more configurations with more processing power up to 122,500 LUTs, Tate said.
Flex Logix is aiming the technology at a broad array of areas, from networking vendors to wireless network providers to search engine environments, all of which need to address demands for faster services, greater flexibility and rapid upgrades. There also is the cost factor: a 2,500-LUT EFLX will add only 15 cents to the cost of an SoC; a 100-LUT EFLX will add less than a cent.
The company is now offering its 2,500-LUT core design to manufacturers. The technology is being built by Taiwan Semiconductor Manufacturing Corp.’s 28-nanometer process. Tate wouldn’t discuss customers, but said the company has seen a lot of interest in the technology.
Roger Kay, principal analyst with Endpoint Technologies Associates, isn’t surprised. He said Flex Logix is offering an interesting technology that fits in with “an industry that is going in this direction.” Kay also noted that Tate didn’t need the money or the hassles that come with getting a startup running.
“For him to come out of retirement to run this shows his belief that this could be a big thing,” Kay told eWEEK.
The technology makes sense, he said. Devices coming on the market today rely on a lot of chips to get the level of performance they offer. Being able to reduce the number of chips used while still getting the performance and flexibility needed would be a win for device and system makers.