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    AMD Next-Gen ‘Kaveri’ Chips to Ship to OEMs This Year

    Written by

    Jeff Burt
    Published November 12, 2013
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      SAN JOSE, Calif.—Advanced Micro Devices will start shipping its much-anticipated “Kaveri” chips to system makers later this quarter, and executives expect the first notebook and desktop PCs powered by the processors to start appearing in the first quarter of 2014.

      The Kaveri accelerated processing units (APUs) initially were scheduled to ship earlier this year but were delayed. However, speaking here at AMD’s Developer Summit 2013 Nov. 11, Lisa Su, senior vice president and general manager of the vendor’s global business units, said the chips will ship before the end of the year.

      Su said the Kaveri chips will bring improvements over competing processors from larger rival Intel in such areas as graphics capabilities, overall performance and power efficiency. Kaveri also signals a significant step forward in AMD’s heterogeneous computing vision of ramping up the parallel computing capabilities in system through the tight integration of multi-core CPUs and GPUs on the same piece of silicon.

      “We believe this really unlocks a different level of … computing,” Su said during her opening keynote address at the developer conference.

      The demand for greater parallel computing capabilities is building through all levels of computing, from mobile devices and PCs to cloud servers and high-performance computing systems, she said. Driving this demand are such factors as cloud computing, big data and greater mobility. AMD’s APU architecture is aimed at addressing that demand.

      “The days of single-threaded performance are over,” Su said.

      She noted that between 2011 and 2012, AMD shipped more than 80 million APUs, a number she expects to grow to more than 150 million in 2014 and more than 300 million within a few years after that, illustrating the growing demand for such heterogeneous computing capabilities in the industry.

      Kaveri will bring with it several enhancements over the current “Richland” APU that will address the need for greater graphics capabilities. The chips will feature up to four CPU cores—based on the new Steamroller architecture—and eight GPU cores, and the cores will share access to memory via AMD’s HUMA technology. In addition, 47 percent of the Kaveri silicon is devoted to graphics, compared with Intel’s current Core “Haswell” chips, in which 31 percent is dedicated to graphics, Su said.

      Kaveri also will offer features from AMD’s Project Mantle effort, which will give Kaveri-powered PCs the same graphics capabilities that are found in gaming consoles, Su said.

      AMD, to help create an ecosystem around its heterogeneous computing vision, created the Heterogeneous System Architecture (HSA) Foundation. According to Su, Kaveri will be the first APU to support hardware specifications released by the foundation, which enables software instructions to easily be moved from the CPU to the GPU for execution, a capability that AMD executives expect will be made available not only in mobile devices and PCs, but also in servers. New APIs from the HSA Foundation also will enable software developers to create code without having to consider whether it will be run on the CPU or the GPU, Su said.

      Those APIs are part of a larger strategy by AMD and the HSA Foundation to make heterogeneous computing a more developer-centric effort, she said.

      They’re also doing this by ensuring that programmers can use familiar languages—such as Java, C++ and Python—and developer tools when writing to such heterogeneous computing systems.

      AMD Fellow Phil Rogers, who also is president of the HSA Foundation, said during his keynote address that AMD also is rolling out a software developer kit to give developers access to AMD’s APU and GPU components to make it easier to write software to them.

      Jeff Burt
      Jeff Burt
      Jeffrey Burt has been with eWEEK since 2000, covering an array of areas that includes servers, networking, PCs, processors, converged infrastructure, unified communications and the Internet of things.

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