Sun Tips Details Of Gemini Blade Server Chip

PALO ALTO, Calif.—Executives of Sun Microsystems Inc. on Monday divulged more details of “Gemini,” the processor that will power Suns blade servers and low-end workstations beginning in 2004.

Gemini combines two older UltraSparc II cores onto a single die with the JBus unit, used in conjunction with Suns latest UltraSparc III processors. Sun said the Gemini processor will be used in Suns H-series of low-end servers, which are optimized for raw throughput.

Sun will formally describe the chip Tuesday at the Hot Chips conference here.

“Traditionally, weve taken the basic design of the S-series (of scalable servers) and made certain adjustments,” said Harlan McGhan, strategic marketing manager of UltraSparc products at Sun. “We brought it down in price … and adopted it in desktop I-series and blade systems.”

Gemini will bridge Santa Clara, Calif.-based Suns traditional design principles with its new multicore strategy, espoused at the companys spring analyst conference. There, the company talked about “Niagara,” the flagship incarnation of chip-level multithreading, also known as hyperthreading.

Gemini will contain two cores, each capable of operating on a single thread containing four different instructions. Niagara, by contrast, will contain eight cores, each capable of processing four threads of a single instruction. Internally, Sun calls Gemini a 2-1-4 design and describes Niagra as an 8-4-1 design.

“Increasingly, companies are trying to build bigger and more complicated cores, where they extract the measure of a single threads performance,” McGhan said. “Weve given up on that,” at least on the throughput-optimized processors, he said. Suns UltraSparc IV is based on a traditional single-core design.

Because Sun simply integrated the UltraSparc II core with a JBus interface, the company completed the design in two years&151;still an internal record for the 80 million transistors the chip will use, McGhan said. Niagara, meanwhile, was largely designed by the Afara Microsystems design team Sun acquired in 2002.

An on-chip DDR-1 memory controller will support between 256MB and 16GB of ECC memory per CPU, McGhan said, for a total of 4.2GB per second of memory bandwidth. Local memory latencies will be on the order of 96 nanoseconds, he said.

Initially, the Gemini will be designed to run at 1.2 GHz at an operating voltage of 1.3 volts; each core will use its own 512KB cache, he said. At 1.2 GHz, the entire Gemini chip is expected to consume 32 watts using a 130-nm process.

However, Sun will also allow customers to lower the operating voltage to 0.9 volts, cutting the frequency to 900 MHz. Doing so will also cut the chips power consumption by 25 percent, McGhan said. “I dont believe any other product can offer this, outside of embedded processors,” he said.