ARM Unveils New CoreLink Interconnect

The new mesh network interconnect and memory controller will help drive ARM's SoC architecture deeper into such markets as HPC and self-driving cars.

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It's been three years since ARM released its last interconnect technology to support its low-power chips. Now the company is running out the third generation of its backplane to help push its silicon in a broad range of markets, from data center infrastructure and high-performance computing to emerging spaces like 5G networks, autonomous vehicles and virtual reality.

The two key parts of the new backplane technology are the CoreLink CMN-600 Coherent Mesh Network interconnect and CoreLink DMC-620 Dynamic Memory Controller. With the new backplane, systems-on-a-chip (SoCs) based on the 64-bit ARMv8-A architecture will have the high data throughput and low latency capabilities that are crucial to these current and newer workloads in the increasingly cloud-centric world.

According to Jeff Defilippi, product manager of interconnect technologies at ARM, networks are under increasing pressure by these applications and use cases to deliver better speeds, capacity and latency. At the same time, acceleration technologies—from GPUs to field-programmable gate arrays (FPGA) to digital signal processors (DSPs)—are being used more to help drive system performance while keeping power consumption manageable.

Users also are looking to put more of the compute and other capabilities out at the network edge, closer to the systems and devices in use, Defilippi told eWEEK.

"A lot of people are trying to figure out how to do acceleration," he said.

For example, high-performance computing (HPC) environments are turning to GPUs from Nvidia and Advanced Micro Devices, x86 co-processors from Intel and FPGAs to help boost the capabilities of their systems. ARM is looking to extend the reach of its SoC designs into such markets while keeping an eye on emerging technologies.

ARM officials said customers can use the coherent mesh network to bring all of these disparate parts together. The dynamic memory controller integrates ARM's TrustZone security technology, supports one to eight channels of DDR4-3200 memory and 3D stacked DRAM for up to 1TB per channel, they said.

Bringing all this together will give users the tools they need to more quickly get their offerings to market, Defilippi said. ARM's Socrates system IP tooling boosts the design of ARM-based SoCs that include the coherent backplane, and users can take advantage of the CoreLink Creator product to automate the building of custom mesh interconnects.

A new technology, Agile System Cache with intelligent cache allocation, can improve the data sharing between processors, accelerators and interfaces.

"We're working to enable partners to build their products faster," he said.

System designers can scale the SoC designs from one to 128 ARM Cortex-A CPUs, and can see higher frequencies (2.5GHz and up), 50 percent lower latency, five times the throughput and more than 1TB/s of sustained bandwidth.

Defilippi said 64 cores will be the "sweet spot for [system makers] going forward," and noted the partnership between ARM and chip foundry Taiwan Semiconductor Manufacturing Corp. (TSMC) to develop a 7-nanometer FinFET chip manufacturing process. The companies, which announced the extended partnership in March, already are working together on 16nm and 10nm processes.

In addition, the new backplane technology will support the CCIX standard for coherent multi-chip processor and accelerator connectivity.