Cavium officials more than a year ago embraced ARM’s 64-bit architecture for its ThunderX line of server processors. Now the vendor is doing the same with its new line of Octeon TX chips for embedded products in such areas as networking and storage.
The company on May 2 introduced the new portfolio of systems-on-a-chip (SoCs) that made up four product families, all of which are based on 64-bit ARMv8.1 cores. Cavium’s previous Octeon chips were based on the MIPS64 architecture. The MIPS products reportedly will continue being produced, with the new ARM-based SoCs expanding what Cavium can offer.
ARM designs low-power SoCs, and then licenses those designs to a broad array of partners, from Qualcomm and Samsung to Cavium, Applied Micro and Advanced Micro Devices. The company’s chip designs are found in most smartphones and tablets, and for the past several years, ARM officials have been pushing to move up the ladder and get their architecture into the data center.
Most of the attention to the effort has centered on servers, and vendors like Cavium, Applied Micro, AMD, Qualcomm and others have either put ARM-based server SoCs on the market or are developing them. However, ARM officials have said they see a role for their low-power designs in a wide range of data center systems, including networking and storage appliances.
According to Steve Klinger, general manager of Cavium’s Infrastructure Processor Group, his company’s new product line is an example of what can be done with the ARM architecture.
“The wide range of products in the Octeon TX ARM 64-bit product line builds upon this success [of the company’s MIPS Octeon SoCs] and expands the use of these products into control and embedded processing applications that leverage the fast-growing ARM ecosystem and breadth of open-source initiatives,” Klinger said in a statement.
The Octeon TX portfolio includes four product families—the CN80XX and CN81XX (one to four ARMv8.1 ThunderX cores and up to 2MB of last-level cache) and CN82XX and CN83XX (eight to 24 cores, up to 8MB of last-level cache). The chips will enable Cavium to get into control plane applications areas in networking and storage for enterprises, service providers and data centers, they said. The chips’ ability to run multiple concurrent data and control planes at the same time will have applications in a wide range of areas, from security and router appliances to software-defined networking (SDN) and network-functions virtualization (NFV), service provider customer-premises equipment (CPE), storage controllers and gateways for the Internet of things (IoT).
The network is under pressure from such trends as big data, mobility, the IoT, the cloud and the massive amounts of data mirrored across the cloud and enterprise, and there is growing demand for them to become more scalable, agile, open and application-centric. The control plane needs to be able to run commercial software distributions (such as Red Hat Enterprise Linux, Canoncial and Java SE) and open-source applications, such as OpenStack, OpenFlow and Quagga, Cavium officials said.
Businesses also want the data plane to simultaneously support multiple high-performance applications for firewalls, content delivery, routing and traffic management, they said. There also is increased demand for bandwidth and the growing security threats.
While the current MIPS-based SoCs are being used in data plane applications and the control plane with embedded software, control plane applications that need a broader software ecosystem have found it in the x86 architecture used by Intel and AMD. Businesses embracing open, service-centric networks are looking for options that offer lower cost and a wide ecosystem, which Cavium officials said the ARM architecture offers.
The new Octeon TX SoCs combine what the MIPS-based offerings do with the ecosystem, virtualization, open-source support and optimized ARMv8.1 CPU cores from the ThunderX portfolio. They also include Cavium’s NitroX V security processors.
The SoCs with one to four cores will begin sampling this quarter, while those with eight to 24 cores will sample starting in the third quarter.