Chip Makers to Outline Road Maps

Performance increases and power management will be key issues at the Microprocessor Forum, where IBM will tout Power6 while AMD will talk up quad-core Opterons.

The industry is getting a glimpse of the not-so-distant future for microprocessors.

At the Microprocessor Forum in San Jose, Calif., Oct. 10, engineers from Advanced Micro Devices, IBM, Fujitsu and Sun Microsystems will give presentations about their new generation of processors that will be released in 2007.

Key to all the work being done is the need to pump up the performance of the chips while keeping the energy consumption relatively level with the current processors, said Charles King, an analyst with Pund-IT Research.

"The next-generation themes include significant processor performance enhancements working hand-in-hand with significant power enhancements," said King, in Hayward, Calif. "These are the things that are resonating with the market. Performance continues to improve substantially, and continues to get there without having to pay a power premium."

IBM, of Armonk, N.Y., will continue the slow release of details of its upcoming Power6 processor, due out in the middle of next year. The technology giant unveiled a number of details at the International Solid-State Circuits Conference in February, most notably that the speed of the processor will more than double the frequency of the Power5, coming in between 4GHz and 5GHz, but will consume about the same amount of power.

/zimages/2/28571.gifIBM rolls out energy-efficient PowerPC chips. Click here to read more.

Brad McCredie, IBM fellow and chief engineer for Power6, said that at his Microprocessor Forum presentation he wont be more specific about the chips speed—engineers are hitting their frequency targets in tests but havent decided what the points will be when it ships—but instead will focus on flexibility and reliability features, as well as some of the system energy management offerings.

"Customers have all said they dont really care what frequency the chips come in at," McCredie said in an interview with eWEEK before the conference. "They care about performance improvement. … They want to know that the hardware will improve the performance of their applications."


Power6, built using IBMs 65-nanometer manufacturing process, rather than the current 90-nm, doubles the frequency of its predecessor but keeps the instruction pipeline at the same depth, rather than growing it, which is how most chip makers often speed up chips. The move means that IBM is able to crank up the speed without adding to the amount of time it takes for an instruction to get through a computation, which inhibits performance.

IBM also is integrating decimal floating point accelerators into the processor, which improves the performance of applications that involve decimals. Normally such work is done through software, McCredie said.

"Doing anything in software takes a lot of instruction and a lot of cycles," hindering application performance, he said. In one test, with telecommunication billing software, application performance improved by four to seven times, he said.

Reliability features include the chips ability to check every computation in the processor and to automatically retry errors. If the retry works, then the computation continues. If there is consistent failure, then the workload is moved to another CPU.

/zimages/2/28571.gifClick here to read about multicore PowerPC chips.

IBM also is designing flexibility into the chip so that it can run in systems both large and small, playing into IBMs eCLipz plan to have a common processor architecture for its widespread server lines, including Systems i, p and z. The 65-nm manufacturing process plays into the energy efficiency, McCredie said. In addition, the chip can be configured for high or low voltage depending on the application needs, enabling the platform to scale, he said.

There also are multiple memory controller, SMP bus and Level 3 cache configurations, he said. In addition, Power6 will feature high-bandwidth memory and fabric I/O, which will help scale the processor.

"We can scale the chip up and down the server product line," he said.

As for virtualization, Power6 will be able to support up to 1,024 partitions and the virtual partitioning of memory.

Pund-IT analyst King said IBM appears to be making the right moves with Power6.

"Doubling the performance without increasing the power envelope is pretty amazing news," he said, adding that the other features are important as well, such as bringing floating-point capabilities onto the hardware. "Its not just more speed, but it allows people to do the kind of business they couldnt have done before."

It also illustrates the work that is still ahead of Intel as it works to improve its Itanium 2 processor. Intel, of Santa Clara, Calif., this year released its first dual-core chip, dubbed "Montecito," which supporters said brought the architecture in line with Power5 capabilities. Power6 is an indication that "the benefits of Montecito could be short-lived," King said.

Next Page: The battle for quad-core.