Version 2.0 will increase the aggregate throughput approximately 75 percent, from 12.8GB per second to 22.4GBps through the inclusion of three new speed grades. Sources expected that the first products using the specification could begin shipping in the second half of 2004.
Although usually associated with Advanced Micro Devices Inc.s line of Opteron and Athlon 64 microprocessors, the HyperTransport CPU-to-I/O interface has become a fundamental part of many platforms, including Apple Computer Inc.s latest PowerPC G5 systems, Nvidia Corp.s nForce chip sets, and by extension, the Xbox game console from Microsoft Corp.
According to analyst company IDC of Framingham, Mass., the number of HyperTransport ports—chips can include more than one port, such as in a server—will essentially double from 2003 to 2004, when the number of ports is expected to grow from about 40 to 90 million. By 2006, the number of ports should increase to a little over 200 million, the firm predicted.
While industry attention will likely focus on the increase on clock speed, the updated interfaces ability to map to PCI Express host bus adapters will likely prove more important, one analyst said. Mapping will allow the familiar interface registers and control methods used to control PCI Express devices to be used with HyperTransport, greatly simplifying the software development that accompanies new hardware.
"Mapping—thats actually a big deal," said Dean McCarron, an analyst with Mercury Research in Cave Creek, Ariz., who said he had not been briefed on the technology. "Its a big deal to recycle software infrastructure." The same principle would be even more useful in enterprise-class applications, where the budget is exponentially larger.
HyperTransport 2.0 will add three new speed grades: 2.0, 2.4, and 2.8 gigatransfers per second, with clock rates of between 1.0GHz and 1.4GHz, sources said. Current HyperTransport 1.0 implementations run at speeds up to 800MHz. However, the width of the bus has been left unchanged in Version 2.0; each unidirectional bus can be 2, 4, 8, 16, or 32 bits wide.
According to sources, the updated interconnect will include several minor electrical enhancements, including a more sensitive receiver. The protocol uses a technique called "de-emphasis," where the amplitude of a signal is reduced if one bit is the same as the previous bit.
In the past, PCI Express and HyperTransport were considered competitive standards. Although open to the industry for royalty-free licensing, PCI Express and HyperTransport were championed by Intel Corp. and AMD, respectively.
"Hopefully, people will now finally realize that they arent competitive," one source added.
Meanwhile, the Sunnyvale, Calif.-based HyperTransport Technology Consortium late in January appointed Mario Cavalli, former semiconductor industry executive, to serve as General Manager.