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The HyperTransport Consortium announced Version 3.0 of the technology on April 24, increasing the link throughput speed and physical distance, and adding an “unganged” mode that can split the available bandwidth into two distinct channels.
Backplanes and components designed around the new backwards-compatible specification will be able to achieve throughputs of up to 2.6GHz, or 20.8GB per second, via either an 8-bit or 16-bit interface.
HT 3.0s performance is slightly less than double the 1.4GHz, 11.2GB throughput allowed by HyperTransport 2.0.
Although HyperTransport is used by the Athlon consumer microprocessor family designed and manufactured by Advanced Micro Devices, the new standard was primarily designed for servers.
The HyperTransport Consortium, which oversees the specification, is officially [platform-]agnostic, although AMD executives participated in a briefing with reporters.
“Its a massive effort, essentially shifting high-performance compute platforms all the way to off-the-shelf processors and interconnections,” said Mario Cavalli, general manager of the HyperTransport Consortium, in an interview. “Its the wave of the future, in a sense.”