IBMs upcoming Power5 microprocessor will enable administrators to easily switch back and forth from multi-threaded to single-threaded mode, and will dynamically shift power within the chip as needed by the work being done.
The features are part of the Simultaneous Multi-threading technology, or SMT, that IBM is putting into the chip, which is due for shipping in the first half of 2004. Systems containing the chip in the companys eServer iSeries and pSeries will be rolled out throughout the end of 2004, according to Mark Papermaster, director of microprocessor design for IBMs Systems Group.
IBM officials are scheduled to make a presentation Tuesday regarding the chips SMT capabilities at the Hot Chips microprocessor conference in Palo Alto, Calif.
Papermaster said the SMT technology in the 64-bit dual-core Power5 will effectively boost user performance fourfold. In the chip, each core will be able to handle two threads simultaneously.
“In the end, we got the implementation [of the SMT] to convince operating systems to see four virtual processors on a single chip,” Papermaster said.
He said IBM researchers were able to manipulate the chip to ensure there were ample resources inside the microprocessor to provide sufficient workflow registers and bandwidth capabilities.
A key mechanism is the ability to dynamically switch the chip from a multi-threaded to single-threaded mode, he said. If an application programmer wants all the processors resources devoted to a single thread, he needs only to insert an instruction call, Papermaster said.
In addition, the chip automatically can sense the work it is being asked to do, and can dynamically shift energy resources toward that job as needed and away from areas where demand is less, Papermaster said.
“The programmer doesnt have to do a thing,” he said. “It will automatically adjust where the power goes.”
Papermaster said more details about the Power5 chip will be released throughout the rest of the year.
