Intel Exec Runs Down New Itanium Roadmap

Intel VP Mike Fister on Wednesday presented a broad overview of the company's enterprise processor roadmap to the Intel Developer Forum audience. He also offered more details of the 64-bit Xeon extensions.

SAN FRANCISCO—Intel Corp. on Wednesday presented a broad overview of its enterprise processor roadmap here at the Intel Developer Forum. The companys forthcoming lineup featured a slew of new code names for the 64-bit Itanium processor.

Mike Fister, vice president and general manager of Intels enterprise group appeared made a special effort to detail Intels Itanium shipment data, in light of the companys Tuesdays disclosure of 64-bit extensions for its Xeon line on Tuesday.

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According to Fister, Intel shipped about 100,000 Itanium units last year. "[A hundred thousand] in a risk-managed environment is a lot," Fister said, attempting to quell doubts that the technology has struggled.

Fister also invited senior executives from Dell Computer Corp., Hewlett-Packard Corp., and IBM on stage to testify to the success of Itanium in their businesses.

Fister outlined a detailed Itanium roadmap through 2005 as additional proof that the architectures future rests on solid ground.

Currently, the Itanium has been designed for two tiers: chips designed for one and two-processor systems, as well as products for four-way systems. The lines run at clock speeds between 1.0 and 1.5-GHz, with a cache size of 4 megabytes.

However, Intel has made changes to this strategy. For example, the forthcoming "Madison 9M" Itanium 2 processor will run a dramatically larger cache, 9MB in size. And, the shipping, low-voltage "Deerfield" version, is designed to enable the Itanium to penetrate more high-density systems.

The architecture received a boost of confidence from Shane Robison, chief strategist and chief technical officer at Palo Alto, Calif.-based Hewlett-Packard. "So what do we see with Itanium? We see a platform with the best price-performance at the high end of the architecture. It gives us true 64-bit capabilities for scalable mission-critical apps."

"Well have Itanium on NonStop and Integrity and Proliant—on industry-standard platforms," he added.

Later in 2004, Intel will ship "Fanwood", the successor to the Deerfield chip. However, Fanwood will be designed for both the mainstream two-way as well as low-voltage markets, Fister said. Fanwood LV will run at 1.2GHz, and the mainstream chip will run at 1.6GHz. Both chips will use 3MB of cache.

Moving into 2005, Intel will ship "Montecito," a previously-announced processor that will integrate two processor cores on a single die and 24MB of cache. The processor will be built on a 90nm process.

Below Montecito will sit "Millington," a new processor designed for both the mainstream and low-voltage applications. Fister did not disclose Millingtons speed.

Beyond Millington, Fister said, will lie Intels next-generation cores: "Tukwila," a multicore Itanium designed by the engineers who created the Alpha chip; and "Dimona," a two-way chip based on Tukwila, as well as a low-voltage version of Tukwila.

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