Intel Execs Run Down Enterprise Processor Roadmap

Intel officials on Tuesday detailed some of the company's product roadmaps for both 32-bit and 64-bit processors aimed at the enterprise market.

A day before Intel Corp. will present its fourth-quarter earnings, executives ran down for analysts the companys product roadmaps and progress in the enterprise market.

Tied down by quiet-period constraints, Intel Senior Vice President and General Manager Mike Fister recapped older enterprise roadmaps in a "state of the enterprise" speech delivered Tuesday in San Francisco. A new focus for the company, power management for enterprise processor, went largely underplayed.

In all, 2003 represented a year in which Intel moved forward on several fronts. "Im not sure its safe to say that 2003 was the year of anything specific or not," Fister said. In 2004, "all kinds of new stuff is coming," he said.

During the first half of 2004, Intel plans to begin shipping its IA-32 execution layer for Itanium, which Intel said will allow an Itanim-based server to process 32-bit code at 50 to 70 percent of its normal clock speed.

In addition, Intel plans a to increase the cache size of its Intel Xeon MP to 4MB, and enhance its dual-processor Xeon as well, most likely with an increase in speed of the front-side bus.

Fister said that 32-bit "Nocona" processor platforms with the "Tumwater" and "Lindenhurst" chipsets will begin shipping in the second quarter, Fister said, complete with DDR-2 memory, PCI Express slots, a faster front-side bus and dual Gigabit Ethernet connectors.

/zimages/5/28571.gifIn November, Intel officials released roadmaps for many of its enterprise and consumer processor lines. Click here to read more.

IBM will also begin shipping a 4-way Xeon blade, while Hewlett-Packard Corp. plans a two-way Itanium module, Fister said. Intels own Xeon blade, code-named "McCarran," is due in the first quarter, he said.

The coming year will see a move toward 800-MHz front-side bus speeds as well as the shift toward the "Prescott" generation of processors, using Prescott New Instructions, or PNI, Fister said. In 2005, Intel will begin rolling out processors with two processor cores on a single die.

Adding 64-bit capabilities to the 32-bit Xeon is unlikely, said Lisa Graff, director of enterprise processor marketing at Intel. "Theres some confusion here that 32-bit and 64-bit are two different market segments and thats not the case," she said. The processors are differentiated by scalability and other features; 32-bit and 64-bit "are just one feature," she said.

Adding 64-bit capabilities simply adds a larger address space, Graff added. "Performance comes from how you architect the CPU," she said.

However, the level of Intels success in the enterprise market is not assured, especially with regards to its 64-bit processor, Itanium. Analyst firm International Data Corp. of on Tuesday lowered its 2007 Itanium revenue forecasts from $8.7 billion to $7.5 billion.


One facet of Intels strategy will be also beef up power management in its processors aimed at enterprise applications.

In 2004, Intel will add the ability for the processor itself to begin managing its own power consumption, similar to the "SpeedStep" power-management technology Intel has added to its mobile line.

In addition, expected in 2005 is the capability to let users define their own power thresholds. At that time, next-generation parts will allow data-center managers to remotely monitor and manage the power a processor consumes, according to an Intel presentation accompanying Fisters speech.

However, Fister did not discuss the power enhancements.