Intel Shows Off 50-Core MIC Chip, Touts Xeon E5

Intel unveils the first of its MIC chips, the 50-plus-core Knights Corner, and its Xeon E5 "Sandy Bridge" processor, both of which will help the chip maker in its push toward exascale computing.

SEATTLE-Intel executives are showing off the first working samples of its Knights Corner silicon, a key technology in the chip maker's drive toward exascale computing.

Rajeeb Hazra, general manager of Intel's Technical Computing Group, held up a Knights Corner chip during a press conference Nov. 15 here at the SC 11 supercomputing show, telling analysts and journalists that Intel has some chips running test systems. He also later showed off a test system running at the conference.

"They're in our labs and working," Hazra said.

Intel officials are using the SC 11 show to shine a light on two key parts of its technical computing push: the Many Integrated Cores (MIC) initiative-of which Knights Corner is a part-and the new Xeon E5 processor, a fast-ramping product that already has found its way into 10 of the systems on the list of the 500 most powerful supercomputers, which was released at the conference Nov. 14.

Both chips are examples of the premium Intel is putting on the technical computing space, which includes supercomputing and high-performance computing (HPC), Hazra said. Technical computing has grown to account for about a third of Intel's overall data center business.

The MIC initiative is designed to address the increasing demand in the HPC and supercomputing space for parallel processing. The drive within the computing community is toward exascale computing, which will enable new and more powerful applications from a wide variety of industries, from manufacturing to health care to energy. However, power consumption is a key hurdle in that effort. Chip makers such as Intel, Advanced Micro Devices and Nvidia are looking for ways to increase a system's performance while making them more energy-efficient.

Nvidia and AMD are using less power-hungry graphics processing units (GPUs) as application accelerators, enabling them to work with a standard CPU to boost performance and enable faster parallel computing while keeping power consumption down. During his keynote address at the SC 11 show Nov. 15, Nvidia President and CEO Jen-Hsun Huang said that, to achieve exascale computing while staying within a 20-megawatt envelope, a system will have to rely on GPU accelerators.

Supercomputer users also are embracing the idea of accelerators. Thirty-nine of the world's fastest supercomputers use accelerators, more than twice the number that was on the Top500 list in June. Analysts from Intersect360 Research say the accelerator push will continue, and currently Nvidia GPUs are the dominant accelerator technology. However, they said, the GPUs will be challenged by Intel's MIC in the years to come.

Hazra and other Intel executives are saying their MIC initiative will help them achieve their goal of reaching the exascale level by 2018, and will be easier than GPUs for researchers and scientists to embrace because it will be based on standard x86 architecture, eliminating the need for users to optimize their applications for GPUs.

The 22-nanometer Knights Corner chip will have more than 50 cores and will work with the CPU to create a complete parallel computing environment and accelerate the performance of applications. The chips are expected out sometime next year, though Hazra was not specific about when they will be released.

"We don't build chips ... and then hold on to them for years," he said, declining to discuss the chip's frequency or wattage.

However, Hazra said Knights Corner will offer up to a teraflop (trillion floating point operations per second), equal to the performance of the ASCI Red supercomputer-powered by 9,298 Pentium II Xeon chips-when it was the fastest system in the world in 1997.

"In 15 years, that's what we've been able to do, and that is stupendous," he said.

Robert Harrison, director of the Institute for Computational Sciences at the Oak Ridge National Laboratory in Tennessee, said his organization has been testing Knights Ferry prototype cards-essentially, Intel's platform development kit for the chip-for the past three months with some solid preliminary results.

Harrison also said that despite the efforts of vendors like Nvidia, he doesn't believe that most of the applications that his institution had ported onto Knights Ferry would not be run on general-purpose GPUs due to the cost and complexity associated with optimizing the software for the environment.

Nvidia officials at the show said they are removing the complexity barriers to optimizing applications for GPU-accelerated environments. Nvidia, along with supercomputer maker Cray and other organizations, on Nov. 14 announced OpenACC, with the goal of creating a standard for parallel computing. The group wants to make it easier for researchers, scientists and corporations to run applications in a parallel fashion on heterogeneous CPU/GPU systems by enabling them to outline directives for the compiler, which will then do all the work to optimize the applications for GPU-accelerated environments.

Intel executives said their Xeon E5 "Sandy Bridge" is already making inroads with OEMs, with as many as 400 designs based on the chip in the works. The chip, which offers up to eight cores and began shipping in September, is aimed at such workloads as cloud computing and HPC applications. It will compete with AMD's 16-core Opteron 6200 "Interlagos" chips, which the vendor officially launched Nov. 14.

Hazra said the Xeon E5 will offer 1.3 to 1.7 times the performance of the current Xeon 5690 across all HPC application categories, and all within the same power envelope. Key enhancements to the Xeon E5 include Intel's Advanced Vector Extention (AVX) instructions and integrated PCI Express 3.0 support, which will improve bandwidth and enable greater scalability.