SAN FRANCISCO—Asking Intel Corp. to talk about its new processor technologies is easy. Persuading the company to talk about when theyll appear in actual hardware is another matter altogether.
Intel executives now call its “Ts” — the grab bag of technologies that enhance a processors performance beyond clock speed — part of the “service-oriented enterprise.” At the Intel Developer Forum here Tuesday, Intels enterprise architects laid out a road map for the companys technology. However, they hedged on when customers could expect features like Vanderpool, the companys partitioning technology, and Silvervale, which will create a number of virtual machines within the processor.
“We believe that going forward the [service-oriented enterprise] will be as relevant as the Internet has been to the enterprise,” said Deborah Conrad, vice president of the sales and marketing group, in a keynote address on Tuesday.
Intels strategy regarding future technology has been to disclose bits and pieces over time, a mix of public relations, relationship building and infrastructure development. Intels reticence this time adds two other volatile elements, executives and analysts said: Intels reluctance to commit to anything it cant deliver, and Microsoft Corp.s rethinking of its Longhorn feature set. Both make a disclosure of Intels enterprise road map more of a jigsaw puzzle than it usually is.
Within Intel, strategic planners are gun-shy about forcing another misstep, such as the delays tied to Intels Dothan mobile processor introduction, the pushout of the 4GHz Pentium 4 into next year, and Intels delay of its LCOS program until 2005. In his keynote address Monday, Intel President and Chief Operating Officer Paul Otellini talked about returning to a “90 percent confidence level” in presenting forecasts to the companys customers.
“Look, wed like to go ahead and tell you more, but somewhere back in corporate people are reading the papers, and the last thing they want to see is, Intel slipped again,” said Phil Brace, director of platforms and services marketing for Intel, in Santa Clara, Calif.
The other piece of the puzzle is Microsoft. To date, Microsoft has publicly committed to supporting just three of the “Ts”: the LaGrande security component Intel is designing, part of the “Palladium” Next-Generation Secure Computing Base; Vanderpool, the partitioning technology; and a third “T,” the EM64T 64-bit extensions, which should be officially supported in a Microsoft release before Longhorn ships. However, Microsoft recently decided to strip the WinFS file system and Avalon graphical interface from the Longhorn package, announcing that both technologies will be available as a separate release.
Intel was expected to talk Tuesday about its Intel Active Management Technology, also known as iAMT. However, that will now take place Wednesday, part of Bill Sius talk on the digital office, Intel representatives said. Siu is vice president of the Intel Architecture Group in addition to overseeing Intels desktop platforms operations.
In a private briefing with reporters, Abhi Talwalkar, vice president of the Enterprise Platforms Group within Intel, said the technology will work to provide a common interface that management software across different vendors can access. “Most vendors have a heterogeneous environment design; they like to pit one vendor against each other,” Talwalkar said.
Intel would like to promote “better manageability through commonality,” Talwalkar said. The iAMT technology will build upon the Server Management Working Group that Intel, Dell and others launched last December. The iAMT technology will be built on standard interfaces, such as IPMI, he said.
“There will be a level of consistency across these silicon ingredients so that theres consistency,” Talwalkar said. Vendors like IBM will have access to these interfaces, he said, although theres a possibility Intel will design OEM-specific modules.
According to Peter Glaskowsky, a former microprocessor analyst for In-Stat/MDR, the technology will involve three components: an iAMT-aware chip set, an iAMT-aware Ethernet NIC and a small amount of additional flash memory. A system could use the technology to issue an OS-independent wake-on-LAN command, for example, minimizing the amount of power necessary to power the system.
The Silvervale virtualization technology, meanwhile, “will be a key system strategy for IT managers,” Talwalkar said. The dual-core Montecito technology has booted this technology already, he said. Although companies like VMWare offer technologies that are on the surface similar to what Silvervale will offer, “all the value that VMware is offering is through software emulation,” Talwalkar said. VMWare will add value “above and beyond” what Intel is offering, he said.
In 2005, Intels enterprise will once again be split between its Itanium and Xeon processors. The problem is that Intel is being much more forthcoming with its Itanium road map than its Xeon processors.
For example, Intels low-voltage, dual-socket-capable Itanium 2 and “Fanwood” low-voltage processor will give way to two processors, the Millington and the dual-socket capable Montvale chip. Both cores will have low-voltage skews, Talwalkar said. The Montvale will also be available in a multisocket configuration, splitting time with the Montecito, Intels first dual-core chip. Both Itaniums will be supported by the E8870 chip set. Beyond 2005, Intel will ship the “Dimona” dual-socket Itanium core and the “Tukwila” for multiway systems.
Intels “Bayshore” program was canceled a short time ago, Talwalkar said, sacrificed to bring the Xeon and Itanium platforms closer together in 2006 and 2007.
Intels Xeon road map is much less clear. The Xeon MP line will yield the Cranford, Potomac and Tulsa processors in 2005, based on the Twin Castle chip set. Future Xeons will include the “Whitefield” processor. Whitefield was primarily designed in India, Talwalkar said, although he declined to comment on whether it will lift low-power technology from Intels low-voltage mobile chips.
However, Intel flatly refused to publicly disclose the next-generation Xeon or supporting chip set beyond early 2005, when the Irwindale, a Nocona Xeon chip with a larger 2MB of cache, will ship. When asked, an Intel spokeswoman told a reporter that she “would get back to him on that.”
Intel did not disclose which of its processors would be dual-core enabled. The road map, however, did outline a laundry list of technologies that could be included: the Pellston cache error-checking technology; the Foxton performance-boosting technology; Dothan-style power management; Silvervale; and the new iAMT technology. According to the road map displayed by Talwalkar, the Vanderpool virtualization, multicore, and enhanced I/O and memory were listed under “future technologies.”
Behind the scenes, however, Intel is working with OEMs and other partners to make its new technologies a reality. “Make no mistake, software developers and engineers are working to develop a working ecosystem with us,” Intels Brace said.
Check out eWEEK.coms Infrastructure Center for the latest news, views and analysis on servers, switches and networking protocols for the enterprise and small businesses.