SuVolta, a startup that builds technologies used in the development of semiconductors, is touting a new transistor technology that officials say can reduce the power consumption in processors by 50 percent or more without impacting performance.
The CMOS technology, which SuVolta calls Deeply Depleted Channel (DDC) low-power transistor technology, essentially reduces the variations in power needs of individual transistors within the chip, reducing electrical waste and making voltage requirements more predictable. The result is significantly less power consumption-as high as 80 percent, when DDC is coupled with advanced voltage-scaling techniques-but without lowering the chip’s performance.
Such metrics are what chip makers are aggressively pursuing in their systems-on-a-chip (SoC) technologies to meet the driving demand for greater performance, energy efficiency and battery life in mobile computing devices like smartphones and tablets, as well as embedded devices and storage appliances.
Currently, the mobile device market is dominated by the likes of Samsung Electronics, Qualcomm, Nvidia and Texas Instruments, which build chips based on designs from ARM Holdings. However, the world’s dominant chip maker, Intel, is pushing its way into the space with its x86-based Core and Atom platforms, and expects its technology to appear in a growing number of smartphone, tablet and ultrabook designs in 2012.
However, SuVolta executives have argued that their DDC technology-part of the company’s larger PowerShrink platform, which was first introduced in June-has a number of advantages over Intel’s efforts, particularly in areas of cost and efficiency.
SuVolta officials this summer talked about the numbers that the PowerShrink CMOS platform could offer-not only the 50 to 80 percent drop in power consumption, but also the fact that the technology can work using half a volt on the chip circuitry, rather than the 1 volt normally seen on chips-but did not elaborate on the details.
That changed Dec. 7, when officials with SuVolta and partner Fujitsu Semiconductor presented the technology at the 2011 International Electron Devices Meeting (IEDM) in Washington, D.C. Fujitsu is integrating PowerShrink into its low-power processor technology. Fujitsu already has demonstrated the technology on some products, and chips with the SuVolta technology are expected to hit the market in the second half of next year.
“SuVolta’s technology, which we have proven in silicon, has generated a tremendous amount of interest in the semiconductor industry,” SuVolta President and CEO Bruce McWilliams said in a statement. “We are now disclosing the details of our DDC transistor technology so that the industry’s technologists can envision how SuVolta’s technology can lower power consumption, can allow lower supply voltage, and can enable process scaling to sub-20 [nanometers].”
SuVolta’s DDC technology calls for adding elements called dopants to several areas of the transistor, making the voltage requirements in those areas more consistent and more efficient.
The PowerShrink platform works well with chip-making processes already in place, according to SuVolta officials, which they said helps keep production costs down by enabling the chips to be built using existing fabrication facilities. This is an advantage over efforts by the likes of Intel. With its 22nm “Ivy Bridge” platform coming out in 2012, Intel is introducing its 3D Tri-Gate transistor architecture, which is designed to significantly drive up both performance and power efficiency. However, SuVolta officials have said that Intel’s design is both complex and expensive, which opens up opportunities for technologies like theirs.
However, despite Intel’s relatively late start in the mobile computing space, some analysts expect the company to become a significant player, given its large R&D budget and massive and powerful fabs.