Epic Challenges Ahead for Intel

At the time that Intel chose to explore the path that led to Itanium, the popular but complex x86 architecture was looking to many chip designers like a technical dead end. As things turned out, the admittedly twisty road to a 64-bit x86 was smoother and faster than it initially appeared, and it certainly led to a destination that enterprise buyers greatly preferred.

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Advanced Micro Devices placed a major bet that enterprise preference for software continuity would trump the theoretical advantages of a bottom-up reinvention of mainstream microprocessor-based computing. AMD won that bet. After explicitly denying (as recently as 2002) any plans to do its own 64-bit extension of the x86, only two-and-a-half years ago did Intel admit the obvious—that the opportunity cost of refusing to do so would be a devastating mistake.

Meanwhile, the daring detour to Itaniums Explicitly Parallel Instruction Computing has proved to be an (ahem) EPIC odyssey. Even the mythic journey of Odysseus took only 10 years, but its now been 12 years since Intel and Hewlett-Packard announced the joint initiative that led to the October 1997 announcement of what was then called the Merced IA-64 microprocessor.

Crucially, Intel announced in 1997 that “Merced processors will run all the software that currently operates on 32-bit Intel processor-based machines.” Buyers took this to mean that IA-64 machines would run x86 code at speeds that at least remained competitive with the still-advancing state of the art of the native x86, but even Intel (let alone AMD) soon dashed that hope by finding more headroom for faster clock rates and higher levels of concurrency on Pentium-compatible chips.

EPIC seeks to identify concurrency opportunities at the time that code is compiled, rather than depending on complex silicon to find those opportunities at run-time. An IA-64 executable gives its “explicitly parallel” instructions to what can consequently be a simpler (and thereby potentially faster) processing engine.

The resulting instruction bloat, unfortunately, requires massive cache memories to avoid unacceptable burdens on the main-memory bus, yielding hardware trade-offs that dont appeal to most buyers today. Packaging a competitive Itanium system is therefore a perilous, even if potentially rewarding, journey.

Technology Editor Peter Coffee can be reached at peter_coffee@ziffdavis.com.

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