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Intel Corp. seems to be responding to IT managers who may be happy with gains in processing speed but are looking for more on-die cache.
At its Intel Developer Forum last week in San Jose, Calif., the chip maker rolled out an aggressive road map for its 32-bit Xeon server processors, which will have accelerated time frames, faster speeds and larger cache sizes. That followed the Santa Clara, Calif., companys announcements last month that it is accelerating delivery of some Itanium processors built with large amounts of cache.
“[More cache] is important if were crunching a lot of numbers,” said Tim Anderson, IS manager for PED Manufacturing Ltd., a cast maker in Oregon City, Ore., that runs Dell Computer Corp. servers. “If were going against a years worth of data, certainly [a larger cache] is a benefit to the company because all the data is already in the cache. It speeds it up. … Well take all you can get in cache.”
At IDF, Intel said it will ramp up the frequency of the Xeon MP Gallatin processor to more than 2GHz next year and will next year release a Xeon chip, code-named Nocona, that will be manufactured using the 0.09-micron process. Existing chips are built using the 0.13-micron process.
Still, what caught the attention of some Intel users was the increased cache sizes of some processors. For instance, a dual-processor Xeon chip with 1MB of Level 3 cache will ship in the third quarter, and Gallatin will have 4MB of L3 cache next year. Current Xeon chips offer 512KB of on-die cache.
The Xeon news comes a month after Intel rolled out an accelerated road map for its 64-bit Itanium chips, which includes a version code-named Madison that will have 6MB of L3 cache and is due at midyear.
A second version of Madison due next year will have 9MB of L3 cache. Intel also said it was adding dual-core processing to its “Montecito” chip, which promises even larger caches, in 2005.
For Stahls Inc., larger caches are “a big plus,” said Mike Terenzi, director of IT operations at the St. Clair Shores, Mich., company.
“In our business, we have about 80 sales reps doing online ordering,” said Terenzi, whose company uses Dell PowerEdge servers. “Theyre all about speed. The faster they can close one sale and move onto another, the better it is for the company.”
However, even IT managers who look forward to more cache on Intel chips said more cache is not necessary in all instances. For those servers running PEDs e-mail system, for example, “in a sense,” said Anderson, “[more cache] could be overkill.”
Similarly, flooring company Mohawk Industries Inc. sees more benefit in a faster front-side bus and core processor.
The Calhoun, Ga., company runs an IBM eServer x440 system that is powered by eight 1.4GHz Xeon MP processors and will be upgrading to a 16-processor system, said Jevin Jensen, director of technical services at Mohawk.
“Im guessing the people running [enterprise resource planning applications] with large databases … will see some benefit” from the larger cache sizes, Jensen said.
“Our … databases are small to medium-size for specific applications but not ERP. The cache hasnt made a big impact there. I am happy to see Intel continue to increase the front-side bus and hope they bring along the processor gigahertz on the entire Xeon family, too,” Jensen added.
Intels Nocoma chip will debut next year, as will a new Xeon MP chip built using the 0.09-micron process, code-named Potomac. Both Nocoma and Potomac will have chip sets designed for them—code-named Lindenhurst and Twin Castle, respectively—and all chip sets next year will include Intels PCI Express I/O technology.
According to Intel officials, the company has been able to accelerate the design time on the 0.13-micron process from 18 to nine months, enabling the chip maker to move up some of its 0.09-micron design plans.