HILLSBORO, Oregon—Intel executive Rani Borker paced in the front of the room sporting a small button pinned to her that read “I Love My Llama.”
While Borker, vice president and general manager of Intel’s Product Development Group, spoke, the 15 or so journalists and analysts seated in front of her passed around Llama Mountain, a 2-in-1 reference design created by Intel and demonstrated at the Computex 2014 conference in June to show off the kinds of thin and light form factors that will be enabled by the chip maker’s upcoming Core M “Broadwell Y” system-on-a-chip (Soc) architecture.
At a recent workshop held at Intel’s campus here, company officials and engineers talked about the design challenges that had to be overcome to create an SoC that was powerful enough, small enough and energy-efficient enough to run the very thin (9mm or less) and very light fanless two-in-one form factors that Intel was aiming for.
It meant innovating on multiple parts of the chip, from improving the power delivery system and shrinking the board area to reworking the 3D Tri-Gate transistor technology, improving the graphics capabilities and increasing the battery life, according to Borker.
“Across the board, there are a lot of changes,” she said. “There wasn’t just one thing. We really attacked the processor at every single level.”
According to Intel officials, the results are pretty good. With Core M, Intel and its OEM partners will be able to offer fanless two-in-one devices—which can be used as either a traditional PC or as a tablet—based on a 14-nanometer SoC design that comes in a package that is 50 percent smaller and 30 percent thinner than the current “Haswell-Y” chip and offers 60 percent lower idle power, which will increase the system’s battery life. The 14nm design also offers twice the performance-per-watt of previous Intel chips.
Core M also offers twice the reduction in the thermal design power over the current Haswell version, and improved performance.
Intel officials are looking to the Core M as a key part of the company’s strategy to drive two-in-ones and other new PCs form factors into a market that is beginning to see some stabilization after a few years of contracting sales as more money and attention were spent on tablets and smartphones. The company initially expected to begin shipping the x86 chips in late 2013, with Broadwell-powered products hitting the market in the first half of this year. Manufacturing issues delayed shipments of the SoCs, but CEO Brian Krzanich said in May that the chips would be shipped in time to enable OEMs to bring systems to the market for the holiday shopping season.
Sanjay Natarajan, vice president and director of 14nm technology development at Intel, said the new chips are being shipped to OEMs now, and are being produced in fabrication facilities in Oregon and Arizona now, with more production coming next year in Ireland. The rate of usable chips coming out of the fabs is healthy enough to support the multiple 14nm Broadwell products that will be shipping in the first half of 2015, Natarajan said.
More details about Broadwell-Y will be released at the Intel Developer Forum next month in San Francisco, but the Intel officials at the workshop here focused more on the technological challenges that had to be overcome not only to continue shrinking the silicon, but making sure it could support the types of devices they wanted to see come into the market.
The company used an “outside-in” approach, deciding first what form factors they wanted to support—in this case, two-in-ones that are 9mm or less in thickness and do not need fans to keep them cool—and then engineering the SoC to meet those demands, according to Stephan Jourdan, an Intel Fellow and director of SoC architecture for the Platform Development Group.
“Without [the] 14-nanometer [manufacturing process], we would not have been able to reach those fanless designs,” Jourdan said.
Intel Digs Deeper Into 14nm Broadwell-Y SoC for Ultrathin Laptops
Eventually the 14nm Broadwell design will run throughout a range of systems, from PCs to servers, as more of the chip family is rolled out into 2015. “It’s going to cover, eventually, top to bottom,” according to Natarajan.
The new SoC will feature the second generation of Intel’s Tri-Gate transistor architecture, a three-dimensional design first introduced in 2011 that is aimed at improving the chip’s performance while keeping a lid on power consumption. It’s Intel’s version of the FinFET 3D transistor design that other chip makers, including Taiwan Semiconductor Manufacturing Corp. (TSMC), Globalfoundries and Samsung, are working on. Natarajan said that while those other companies are still working to get their first-generation technology completed, Intel is about to launch its second-generation Tri-Gate architecture.
In the latest Tri-Gate technology, Intel reduced the distance between the elements, while also making the “fins” on the architecture thinner and taller than those in the 22nm Haswell chips, reducing the number of fins needed. This helped improve the density and lower the power of Broadwell.
The combination of the 14nm design and new Tri-Gate technology means greater SRAM (static random access memory), and the new transistors offer greater performance and less power leakage than previous generations, Natarajan said. The 14nm architecture also is helping reduce the cost-per-transistor, which he said is “a key trend for Moore’s Law.”
Getting Broadwell to meet the challenge of fanless designs—with thickness of 8mm to 10mm and a 10.1-inch display—required developing an SoC that consume 3 to 5 watts of power. Through optimizations in the 14nm design—in such areas as capacitance, minimum operating voltage and low-voltage transistor performance—Intel was able to deliver twice the power reduction than simply reducing the scale of the chip would bring.
In addition, the second generation of Intel’s Fully Integrated Voltage Regulator (FIVR) and the movement of the 3DL Modules from the SoC’s package substrate to underneath the die improved power delivery in the chip, while Intel also brought enhanced power management features—including enhanced Turbo Boost—improved energy efficiency and performance, according to Jourdan.
In the Converged Core, some of the improvements over Haswell include a larger out-of-order scheduler, a faster floating-point multiplier, faster virtualization round trips and performance features that were designed with a performance to power ratio of 2:1, all of which add up to greater performance and improved energy efficiency.
