SAN JOSE, Calif.—Intel Corp.s enterprise processor road map will evolve into an ever more complex matrix, where customers will be asked to make choices based on multiprocessing and thermal power.
The result will be an enterprise environment where IT managers and enterprise OEMs will design for multiple processor threads running on chips with multiple processor cores, in systems housing multiple processors.
“We can move to a place of multiple threads on a single core and multiple cores on a single package, then multiple processors in a single system,” said Ajay Malhotra, general manager of Intels enterprise marketing and planning group, in an interview at the Intel Developer Forum here. “Reducing computational time from a week to a day … is super exciting.”
On Tuesday, Intel President Paul Otellini added two new names to Intels enterprise road map: “Tulsa,” a 32-bit Xeon that will contain two processing cores, and “Tanglewood,” a multicore Itanium chip. Intel did not disclose when either chip will ship, but the companys new public processor road map does not show either chip shipping before 2005.
Analysts said they suspect that Intel will have to combine two cores on a single die or else lose any speed advantage multicore implementations would offer. When a chip searches for data off-chip in main memory, tens or even more than 100 processor cycles could be wasted waiting for data. Looking for the same data in an on-chip cache can take a fraction of the time, keeping the processor “fed” with data at its most efficient.
“I would have to believe theyre talking about multiple cores on die,” said Peter Glaskowsky, editor of The Microprocessor Report and an analyst with In-Stat/MDR. “It just makes sense.”
Still, Malhotra said, thats not necessarily the case. “It doesnt have to be individual cores on a die—it could be a multichip package,” he said of the Tulsa and Tanglewood. The decision, Malhotra admitted, hasnt been made.
Although the design decision seems esoteric, it could have a real impact on the price of Intels future chips. A chip made out of a single die means fewer chips can be produced per wafer, reducing the amortization of the wafer cost across the individual die. In turn, those costs are passed along to the customer. Divvying up the die may lower performance, but the end price of the chip could be lower.
Intel will make its decision easier by redesigning the Itanium core yet again. Both Tanglewood and Tulsa will be designed around “optimized” Itanium and Xeon cores, respectively, Malhotra said. Tanglewood, at least, will be architected from the Alpha processor design team Intel picked up from Compaq Computer Corp.
Intels 2004 Itanium offerings will include the Madison 9M, optimized for both multiprocessor (four-way) and dual-processor servers. A low-power “Deerfield” Itanium will also ship next year. In 2005, Intel will ship the dual-core Montecito for multiprocessor and dual-processor servers, as well as an unnamed Deerfield follow-on. Tanglewood is expected to contain four cores with two threads per core, said Nathan Brookwood, an analyst with Insight64, of Saratoga, Calif.
Adding the Vanderpool partitioning technology will give IT managers more control over their systems. “Thats why it was so important for them to show the SGI [Altix 3000] system, with 128 Itanium 2s,” Glaskowsky said.
Intels enterprise 32-bit road map has changed little, save for the companys delay of the two-way Nocona until late in the first half of 2004. Intel will fill in its “volume enterprise” segment gap with Xeon processors running at 3.06GHz and above until the Nocona ships at “greater than 3.2GHz” in the second half of 2004, according to the road map.
Previously, confidential Intel road maps have said Nocona would ship in the second half of 2003 using a 533MHz and 667MHz front-side bus. Now, the Nocona and its successor, Jayhawk, are being paired with the Tumwater and Lindenhurst chip sets, which use an 800MHz front-side bus. A “Lindenhurst-VS” chip set will also be offered for the “value segment” of the enterprise space. All three chip sets will incorporate PCI Express and DDR-2 memory.
Intel will re-enter the four-way Xeon space in early 2004 with the launch of the “Twin Castle” chip set, also supporting PCI Express and DDR-II memory. Previously, the company had relied on OEM-designed and third-party chip sets to fill the bill.