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SAN FRANCISCO—Even at Intel, the turtle sometimes wins the race.
The Santa Clara, Calif., chip maker opened its three-day fall Intel Developer Forum, by rewriting the tale of the tortoise and the hare in Intel style.
It pledges to trade processors that flaunt outright speed for those that offer greater efficiency.
It officially abandoned the race to boost clock speeds in favor of honing its next generation of processors, due in 2006, to maximize the amount of performance they deliver per watt of electricity they consume.
The company will achieve its goal of boosting performance per watt by rolling out new circuitry for its desktop, notebook and server chips, which will first arrive in the second half of 2006.
Power consumption has already become a major factor in how notebooks PCs are designed.
Notebook processors must be designed to use less power and produce less heat than desktop or server chips in order to deliver long battery life and fit into the small confines of a notebook chassis.
But power efficiency stands to weigh more heavily in desktop and server designs in the future as corporations demand servers that use less electricity and demand for smaller and less obtrusive desktops rises, Intel executives said at the Forum.
Thus they chose the new approach.
“We realized that power efficiency was critical,” said Stephen Smith, vice president of Intels Digital Enterprise Group, during a briefing at IDF.
Now “Our driving force is low power, high performance and what we call foundation for innovation—some common elements of the technology infrastructure that people can use to design systems and software,” Smith said.
The new architecture, which will span desktops, notebooks and servers for the first time in several years, will focus on getting more work done per clock cycle and favor multiple processor core chips, two elements the executives said will bump up its chips performance while holding down the amount of power they consume.
Next Page: Pipeline assembly lines.
Pipeline Assembly Lines
The new architecture will process four instructions per clock and use a 14-stage pipeline, Smith said during the IDF briefing.
Intels NetBurst architecture, the underpinnings of chips such as its Pentium 4 and Xeon, issues two instructions per clock, while the latest Pentium 4 chips use a 31 stage pipeline, analysts said.
A chips pipeline functions like an assembly line, performing a function at each stage.
Long-pipeline chips such as the Pentium 4, move more quickly through each stage, but do less work at that stage.
Thats where a faster chip might not always outperform a slower processor, given that the slower chips shorter pipeline can be made to get more work done in its fewer steps.
The overhead in circuitry a longer pipeline chip needs also increases its power consumption, versus a shorter pipelines chip, said Kevin Krewell, editor in chief of the Microprocessor Report.
“NetBurst is dead,” Krewell said.
Instead, he likened the new Intel approach to that of the PowerPC chip or Advanced Micro Devices Inc.s AMD64 architecture, the circuitry behind its Athlon 64 and Opteron chips, Intels two main competitors.
Thus the new Intel chips will be “pretty competitive,” Krewell said. “It should be a pretty worthwhile competitor for AMD64 architecture. There will be a closer, toe-to-toe battle between AMD and Intel on a performance per watt basis.”
Krewell predicted the new chips will run at 2GHz to 2.5GHz, where chips such as the single-core Pentium 4 run at speeds up to 3.8GHz and the dual-core Pentium D runs at up to 3.2GHz. But, despite their speed, those chips can consume upwards of 100 watts.
Paul Otellini, Intels CEO said in his opening keynote speech on Tuesday that Intels new architecture chips will consume far less power.
The most power-hungry new-architecture server chip, a dual-core processor dubbed Woodcrest, will consume a theoretical maximum of about 80 watts, about 30 less than the current Xeon line, he said.
Intels forthcoming new architecture desktop and notebook chips, Conroe and Merom, will consume even less, dropping to 65 watts for desktops and 5 watts, respectively.
Smith confirmed that the new architecture will be based largely on the Pentium M, whose structure already lends itself to energy efficiency.
Intels current Pentium M chip, for its part, consumes a maximum of 27 watts and runs at more than 2GHz.
But, compared to the Pentium Ms circuitry, the new architecture will use a longer pipeline.
Intel will splice in some of the elements found in NetBurst, including 64-bit addressing and will use a version of the NetBurst bus, which feeds data to the chip. But the new chips will look more like Pentium Ms than Pentium 4s.
“We put those two things together and added some new innovations—those things together form the basis for the new microarchitecture,” Smith said.
“This is without a doubt the highest performance machine [or chip design] weve built for the… x86 microarchitecture.”
The new architecture also makes improvements in cache management and memory access, Smith said.
Thus chips such as Woodcrest will deliver improvements as high as 3.5 times higher performance per watt and double the overall performance versus Intels current single core Xeons.
Although they will each pack twin cores when they debut in the second half of 2006 Conroe, Merom and Woodcrest will be differentiated for their respective markets.
Conroe, for desktops, and Woodcrest for servers will be available with multiple different cache sizes, creating versions of the chips for different market segments.
For its part, Merom will come with specific features that lower its power for notebooks.
Intel will follow its dual-core chips with quad-core processors.
Among the first will be Whitefield a four-core Xeon chip and Tukwila a four-core Itanium chip, due in 2007, Smith said.