IBMs longtime development strategy for its Power chips has been to build them in a way that enables users to get the most out of software—be it home-grown or third-party.
The new version of IBMs 64-bit processor will be no different, said Mark Papermaster, director of microprocessor design for IBMs Systems Group, in Austin, Texas.
“There is very close participation with both IBM software [developers] and the open-source community,” Papermaster said. “We have to ensure that the features we add to our processors will contribute to [software] performance improvements.”
A key to Power5, which is due in the first half of next year, will be its multithreading capabilities. Multithreading lets a chip run multiple tasks at the same time. Combined with the other performance-enhancing features on the chip, multithreading could translate into a fourfold application performance boost, Papermaster said.
The chip will also allow easy switching between single-threaded and multithreaded mode, Papermaster said.
The architecture for the dual-core Power5—code-named Squadron—will bring logical partitioning into the sub-CPU level, enabling users to run more applications on systems. Currently, a 32-way eServer p690 running on a Power4 chip can be partitioned into 16 virtual servers. According to IBM officials, a 32-way Power5 server will be able to be partitioned into at least 32 virtual systems.
Furthermore, the Power5—which will run at speeds faster than 1.5GHz, although officials have yet to give an exact frequency—will continue to enable users to run 32-bit or 64-bit applications on IBMs AIX operating system or on Linux, even simultaneously.
“As they transition to 64-bit, they now get a choice of operating systems, AIX or Linux, that run 32-bit applications as well as 64-bit,” Papermaster said. “There are no recompilers needed, no translators needed.”
IBM this year will start shipping the PowerPC 970 chip, a 1.8GHz processor aimed at the high-volume space that will offer users the same architectural features as the Power4.
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