Advanced Micro Devices, Oracle and Fujitsu were among the tech vendors that used the Hot Chips 2014 show this week to give more details about their upcoming server processors.
AMD officials released more information about the company’s Opteron A1100 “Seattle” chip, the company’s first venture using ARM’s low-power 64-bit ARMv8-A architecture in a processor aimed at smaller, dense systems designed for hyperscale environments. At the same time, company officials also reportedly said they were considering building custom 64-bit ARM-based server processors for customers.
At the same time, Oracle officials unveiled some of the details in the upcoming SPARC M7 chip, which will feature 32 cores and offer as much as three to four times the performance of the previous generation chip. In addition, Fujitsu officials talked about their on-the-horizon 32-core SPARC64 XIfx processors aimed that the high-performance computing (HPC) space.
AMD officials said two years ago that the company would begin offering ARM-based server chips to go along with its traditional line of x86-based Opterons. ARM-based systems-on-a-chip (SoCs) are found in most smartphones and tablets, but executives for several years have talked about the intention to move into the data center and compete with chip giant Intel, particularly in smaller, energy-efficient systems. Key to the move was the development of the ARMv8-A architecture, the company’s first 64-bit design.
AMD, the largest server chip maker to embrace the ARM architecture, for a year has been talking about the 28-nanometer Seattle processor, which will offer four to eight ARM Cortex-A57 cores, and late last month unveiled a development kit for the chip aimed at developers. At Hot Chips, AMD officials gave more details. The chip, which is due to hit the market by the end of the year, will have up to 4MB of Level 2 cache and 8MB of L3 cache, two 64-bit DDR3/4 channels with error-correction code (ECC) memory, and has eight SATA 3 ports, according to the company.
There also are two 10GBASE-KR Ethernet ports and eight lanes for PCI Express Generation 3, and the chip offers a cryptographic coprocessor to accelerate the processing of encryption and decryption tasks, as well as compression and decompression.
AMD officials in May announced “Project SkyBridge,” which over the next two years will include enabling x86 and ARM chips to run on the same motherboard with few tweaks, and in 2016 will introduce the first of the company’s “K12” chips that will include an ARM-based core developed in-house. AMD will compete against other ARM server chip vendors, like Applied Micro and Cavium, as well as Intel’s low-power Xeon and Atom offerings.
At Hot Chips, AMD officials also said they are considering making custom ARM server chips for customers.
John Fowler, executive vice president of systems at Oracle, introduced the upcoming SPARC M7 processor, which will feature up to 32 cores, up to 2 TB of DDR4 memory, PCIe Gen 3 technlogy, shared L2 cache and up to 64MB of shared and contained memory. It will bring three to four times the performance of the SPARC M6 processors, depending on the workload, and offers more than twice the cores of its 12-core predecessor, which was released in 2013.
It’s also smaller than the M6, being made via a 20nm processor, rather than 28nm. The SPARC M7 also will come with such acceleration technology as in-memory processing for faster performance, and support for “live compression,” which will enable more data to be sent in a compressed format without hurting performance.
When Oracle bought Sun Microsystems in 2010, CEO Larry Ellison insisted that he intended to keep the former company’s hardware line, with the vision of creating systems that were optimized for Oracle’s enterprise hardware. The result has been such systems as Exadata (for database applications) and the Exalogic cloud solution.
Fujitsu officials reportedly spoke about the company’s upcoming 32-core SPARC64 Xlfz chips aimed at HPC systems and—along with two “assistant” cores—offering more than a teraflop of double-precision performance in hopes of fueling its push to petascale computing. The new chips will offer more than three times the double floating-point performance and six times the single floating-point performance of the SPARC64 IXfx.