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Intel has begun shipping a development module that features the company’s latest Xeon E5 server processors and programmable chips that will help customers drive performance while holding down power consumption.
The multichip platform is pairing the 14-nanometer Xeon E5-2600 v4 “Broadwell” processors—launched late in March—with the Arria10 field-programmable gate arrays (FPGAs) from Altera. Diane Bryant, senior vice president and general manager of Intel’s Data Center Group, on April 13 announced during a keynote address at the company’s Intel Developer Forum (IDF) in China that the modules were shipping.
Intel and other chip makers are increasingly relying on accelerators to help improve the performance and energy efficiency of their processors and speed up the workloads that run on them. Nvidia and Advanced Micro Devices offer GPU accelerators. However, the company also is now using FPGAs, which can be reprogrammed through software after they’ve been manufactured. They’re becoming more important for cloud and Web-scale environments, where workloads can change quickly.
Intel for several years had partnered with Altera to take advantage of the company’s technology. Intel now has brought the company in-house, earlier this year completing the acquisition of Altera, which the chip maker bought for $16.7 billion. Intel officials have said the goal is to eventually integrate the FPGAs onto the same die as the CPU.
Intel is not only relying on FPGAs for CPU acceleration. The company also has a growing portfolio of Xeon Phi chips, which are x86-based co-processors that can act either as accelerators or as primary chips. In addition, Intel is partnering with eASIC to bring application specific integrated circuits (ASICs) to custom Xeons to be used in enterprise data centers and cloud environments for such workloads as data analytics and security. The goal is to offer customers a broad range of choices.
Intel officials have said they expect FPGAs will be used in as much as 30 percent of data center servers by 2020. Bryant in China said the combination of the FPGAs and Xeon E5 chips will drive a 70 percent improvement in performance-per-watt to systems.
The executive announced in November 2015 that Intel planned to release the first of its Xeon chips with the FPGAs early this year, adding that the first would ship to the largest hyperscale cloud companies, such as Amazon Web Services, Facebook, Microsoft, Google and Baidu. At the time, she didn’t specify which companies would receive the chips.
The use of accelerators is becoming increasingly popular in a growing number of fields. The high-performance computing (HPC) space for almost 10 years has been using GPU accelerators from Nvidia and AMD to improve their systems’ performance and power efficiency. More than 100 of the world’s 500 fastest supercomputers use either GPU accelerators from Nvidia or AMD or Intel’s Xeon Phis. Microsoft last year announced Project Catapult, an initiative to use FPGAs in servers running with Intel Xeon chips to speed up Bing search results.
In addition, Intel is not the only chip maker turning to FPGAs. Xilinx has been partnering with such vendors as Qualcomm—which is developing ARM-based systems-on-a-chip (SoCs) aimed at servers—and IBM, which is using Xilinx’s FPGAs in Power Systems for such workloads as data analytics, machine learning, network-functions virtualization (NFV), HPC and genomics.
Editor’s note: This story has been changed to reflect that the module will include an Arria 10 FPGA.