Intel engineers are coming to this year’s ISSCC conference with the message that the company’s work on 14-nanometer processor development is paying dividends, and that they can continue to meet the demands of Moore’s Law as they continue to shrink the chips over the next several years.
Over three days at the International Solid-State Circuits Conference in San Francisco starting Feb. 23, Intel engineers will present five papers—with most focusing on technologies found within the 14nm processors—while Mark Bohr, Intel Senior Fellow for logic technology development at Intel, will participate in a panel to talk about driving Moore’s Law down to 10nm and beyond.
In a conference call with journalists and analysts days before the show began, Bohr noted the increasing costs involved in chip development, saying that reducing those costs is important if work on new generations of chips is to continue. However, what Intel has accomplished in its development of the 14nm chips and what it can do over the next several years—10nm and 7nm processors—are proof points that Moore’s Law still has legs, despite some in the industry who have said it is reaching the end of the road.
“Innovation has always been important to the scaling process,” Bohr said, noting such technological breakthroughs as FinFET (what Intel calls its Tri-Gate 3D transistor architecture) and High-K Metal Gate. “It’s an indispensible part of what we do.”
Moore’s Law started off as a prediction in 1965 by Intel founder Gordon Moore, who said that the number of transistors on a chip would double about every 18 months. Over the decades, it has been the driving force behind Intel’s development, with the number of transistors continuing to grow even as the size of the chips themselves has shrunk, leading to computing devices—from smartphones to servers—that run faster and consume less energy.
However, as the transistors continue to shrink in size while the manufacturing costs grow, Moore’s Law—hitting its 50th anniversary this year—becomes increasingly challenged. However, Bohr and other Intel engineers on the conference call said that innovation will enable the chip maker to continue meeting Moore’s Law and driving down the cost-per-transistor for 10nm and then 7nm into 2018. In addition, Intel will be able to reach 7nm without using such expensive technologies as Extreme Ultraviolet Lithography (EUV), Bohr said.
He did touch on such new technologies that could be used for 7nm, such as III-V devices, but stressed the need to balance performance and manufacturing costs. He also pointed to systems-on-a-chip (SoCs) designs, saying that “heterogeneous integration will become increasingly important.” This includes such technologies as 2.5D (where two chips are mounted onto a substrate next to each other) and 3D integration (where the chips are stacked on top of each other).
However, Bohr would not give many details on Intel’s plans, saying the company’s “competitors watch what we do closely.”
The move from the 14nm “Broadwell” chips to 10nm will be aided by some of the troubles Intel had getting 14nm chips out the door. The company had to delay the release the chips by as many as nine months due to testing taking longer than expected.
“We may have underestimated the learning rate,” Bohr said. “That slowed us down more than we expected and thus took us longer to fix the yields.”
Now 14nm production is humming along, and Intel engineers were able to apply what they learned to their work with 10nm. So far, the effort—which includes making the internal testing more efficient and improving the yields more quickly—is working: the Intel engineers said that the 10nm pilots lines are running 50 percent faster than 14nm lines.