Intel has begun sampling its Stratix 10 programmable chips, which the company expects to use as accelerators in data center environments running compute- and data-intensive applications.
In a blog post Oct. 4, Dan McNamara, corporate vice president and general manager of Intel’s Programmable Solutions Group, wrote that company engineers were able to combine the chip maker’s 14-nanometer tri-gate manufacturing process with its HyperFlex fabric architecture to develop a field-programmable gate array (FPGA) that will address the growing demands from end users for more performance and power efficiency as they try to manage the proliferation of smart, connected devices and the huge amounts of data they’re producing.
Intel is aiming the Stratix 10 FGPAs at such workloads as data center applications, cloud computing, radar and imaging systems, and network infrastructure, McNamara wrote.
“We live in a smart and connected world where billions of devices are creating massive amounts of data that must be collected, rapidly processed and analyzed, and available from anywhere,” he wrote, adding that Intel and the Stratix 10 will enable “service providers, data centers, cloud computing and storage systems to satisfy their insatiable demand for higher computational capabilities, lower latency, greater system flexibility and increased power efficiencies.”
With Stratix 10, Intel is delivering twice the performance and more than five times the density when compared to the previous generation of FPGAs, and up to 70 percent lower power than Stratix V FPGAs while providing equivalent performance. There also is up to 10 teraflops of single-precision floating point performance, up to 1TB memory bandwidth that includes integrated High-Bandwidth Memory, and an embedded quad-core 64-bit ARM Cortex-A53 chip.
FPGAs are among a widening group of accelerators used to help speed up the performance of large-scale systems while keeping a lid on power consumption. Accelerators—particularly GPUs from Nvidia and Advanced Micro Devices and x86 Xeon Phi co-processors from Intel—have been used in high-performance computing (HPC) and supercomputing environments. However, with the growth in the number of connected devices and the accompanying data, the rise of cloud computing and the internet of things (IoT), and the increasing amount of video in network traffic, the use of accelerators is expanding.
Intel officials have said they expect FPGAs to be used in as many as 30 percent of all data center servers by 2020.
Intel inherited the Stratix FPGA technology when it bought Altera last year for $16.7 billion. Altera and Xilinx have been the primary vendors behind the development of FPGAs, which have the added benefit of being able to be reprogrammed for different workloads. Intel began shipping Xeon server chips with Arria 10 FPGA accelerators earlier this year. Along with FPGAs and the Xeon Phi co-processors, Intel officials are looking to increase the number of accelerator options by working with eASIC to bring application specific integrated circuits (ASICs) to custom Xeons to be used in enterprise data centers and cloud environments for such workloads as data analytics and security. Intel was a partner of Altera’s before buying the company.
Intel is not the only chip maker turning to FPGAs. Xilinx has been partnering with such vendors as Qualcomm—which is developing ARM-based systems-on-a-chip (SoCs) aimed at servers—and IBM, which is using Xilinx’s FPGAs in Power systems for such workloads as data analytics, machine learning, network-functions virtualization (NFV), HPC and genomics.