Intel officials, seven months after introducing the company’s Xeon Phi coprocessors for high-performance computing systems, are highlighting the technology’s success while giving the industry a glimpse of what will come in the next generation, called “Knights Landing.”
At the same time, the company is expanding the current Xeon Phi portfolio with two new product lines that are designed to give organizations a greater range of choices depending on workload, cost and performance.
The overall thrust of Intel’s message this week at the 2013 International Supercomputing Conference (ISC) in Germany is that the Xeon Phi coprocessors, more than competing graphics accelerators from Nvidia and Advanced Micro Devices, are the better option for high-performance computing (HPC) environments.
“This will be a fundamental accelerator … of high-performance computing going forward,” Rajeeb Hazra, vice president and general manager of Intel’s Technical Computing Group, told journalists on a conference call a few days before the ISC opened.
Nvidia and AMD for the past few years have championed their GPU accelerators as the products needed for organizations that want to ramp up the performance of their supercomputers while keeping their power consumption in check. The systems can offload more highly parallel workloads from the main processor to the accelerators—which are smaller and offer many more cores than primary processors—freeing up the bigger and less energy-efficient base processor to work on the more compute-intensive tasks.
Intel a couple of years ago began working on its Many Integrated Core (MIC) initiative, which resulted in the Xeon Phi, a coprocessor that offers more than 60 cores to essentially do the same job as the GPU accelerators. The key is that—like Intel’s Xeon processors and AMD’s Opteron server chips—the coprocessors are built on the x86 architecture.
Intel officials argue that most programmers already are familiar with the x86 architecture and its tools, so working with Xeon Phi will be easier. Workloads running on Xeon Phi coprocessors have to undergo less recoding than those running on GPU accelerators, they said.
It’s the key point Hazra and other Intel officials at the ISC are making in their argument for what they call “neo-heterogeneity.” HPC environments are going to be heterogeneous, with the use of both processors and coprocessors or accelerators, Hazra said. With Xeon Phi, Intel offers heterogeneity in hardware, but with a common programming model.
Officials for both AMD and Nvidia have countered that the amount of recoding for GPU accelerators is minimal and not a real obstacle to their use, and have said they are not done innovating their products.
The massive Tianhe-2 supercomputer in China—also called Milky Way-2—which now tops the Top500 list as the fastest system in the world, uses 32,000 Xeon E5-2600 processors and 48,000 Xeon Phi coprocessors. In addition, the sixth-fastest system, the Dell PowerEdge-based Stampede at the Texas Advanced Computing Center, also leverages Xeon Phi coprocessors.
Intel Gives Glimpse of Upcoming Next-Gen Xeon Phi
In all, 54 of the 500 supercomputers on the list use coprocessors or GPU accelerators. Eleven use Xeon Phi coprocessors, while 39 use GPU accelerators from Nvidia and three use AMD’s ATI Radeon GPU accelerators.
Intel is expanding its current crop of 22-nanometer Xeon Phi coprocessors beyond the 5100 family—which was introduced in November 2012—with the 7100 product line that offers the best performance and most memory, and the value-focused 3100 family. The 7100 coprocessors, announced at the ISC June 17, include 61 cores at speeds of 1.23GHz, support for 16GB of memory and more than 1.2 teraflops of performance. The 3100 line features 57 cores clocked at 1.1GHz and 1 teraflop of performance.
A new coprocessor for the 5100 family—the 5120D—is optimized for high-density environments.
Partners like supercomputer maker Cray and systems maker SuperMicro announced support for the new Xeon Phi offerings.
On the horizon is Knights Landing, a Xeon Phi offering that will be made via Intel’s 14nm manufacturing process and include the vendor’s 3D Tri-Gate transistor architecture. In addition, it will differ from the first round of coprocessors by being able to be used as either a coprocessor or as a primary processor, according to Hazra.
“It is also a standard CPU,” he said.
Organizations can either use it as a PCIe card-based coprocessor in the same fashion the Xeon Phi currently is used, with the base processor offloading jobs to it, or as a traditional processor installed directly onto the motherboard socket. In that role, it will function as any other CPU while also handling the job of the coprocessor, and will help drive greater compute density, energy efficiency and performance per watt, Hazra said.
Intel also will offer integrated memory on Knights Landing, which will increase memory bandwidth.
Hazra declined to give many details about Knights Landing, and would not say when the product would be released.