Intel is doubling down on core count as it prepares for its next high-end server CPU battle with AMD.
Intel unveiled more details about its next-generation Xeon 7 platform, codenamed Diamond Rapids, at Hot Chips 2026. The company says the processor will scale to 256 P-cores and 1.28 GB of last-level cache in its largest configuration.
That represents a major jump from Granite Rapids, whose top configuration reaches 128 P-cores. Intel is positioning the chip for demanding data center workloads including AI and high-performance computing.
The timing has also shifted. Diamond Rapids was previously expected sooner, but Intel now plans to bring it to market in 2027. The Register reports that the company also dropped planned eight-channel versions, leaving the high-core-count design as the focus.
Intel changes how the chip is built
Diamond Rapids uses up to 22 chiplets divided among 16 core chiplets, four base tiles and two Fabric Hub tiles, according to Intel. Each core chiplet can contain 16 P-cores. Four chiplets sit above each cache-bearing base tile, creating four Compute Building Blocks with 64 cores apiece.
Intel is using its Foveros Direct 3D technology to stack the core chiplets onto the base tiles. It then uses UCIe-S connections through the package substrate to link those compute blocks with the central Fabric Hubs.
The Fabric Hubs handle memory and I/O, allowing Intel to create what it calls a unified memory fabric. Intel chose UCIe-S instead of its EMIB packaging for these longer connections because it says the approach provides more uniform access to the memory hubs.
More memory and faster I/O
Diamond Rapids will support 16 memory channels, with DDR5 reaching 8,000 MT/s and MRDIMMs reaching 12,800 MT/s. Intel lists up to 1.6 TB/s of memory bandwidth. The platform will also offer up to 128 lanes that can be used for PCIe 6.0, CXL 3.0 or UPI 3, plus eight PCIe 4.0 lanes for platform functions.
That combination matters because adding 256 cores without increasing the memory and I/O capacity could leave those cores waiting for data. Diamond Rapids instead expands all three parts of the system together.
New instructions, but one notable omission
Intel is adding AVX 10.2 and Advanced Performance Extensions, or APX. APX doubles the general-purpose register count from 16 to 32, while Intel says recompiling software for the new instructions can reduce memory loads and stores.
The processor will also feature enhanced AMX capabilities for AI workloads. But Diamond Rapids will not support Hyper-Threading, according to The Register. That leaves Intel with 256 physical cores and 256 threads, while AMD's forthcoming 256-core EPYC Venice is expected to support 512 threads.
What eWeek found: Intel is competing on balance, not just cores
The interesting part of Diamond Rapids is not the 256-core headline by itself. Intel is pairing that number with 16 memory channels, 1.28 GB of cache and up to 1.6 TB/s of memory bandwidth.
That suggests Intel is trying to avoid the classic problem of building a huge CPU that cannot keep its cores fed. The real test, however, will come when independent benchmarks show whether the new architecture can turn that unusually large hardware footprint into better real-world performance than AMD's 256-core Venice.
For now, Diamond Rapids gives Intel numerical parity at the top end while introducing a substantially different Xeon design. Its success will ultimately depend less on the specification sheet than on performance, power, pricing, and how well its new architecture handles real HPC and AI workloads.
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